JPS58213341A - 加算回路 - Google Patents

加算回路

Info

Publication number
JPS58213341A
JPS58213341A JP9641882A JP9641882A JPS58213341A JP S58213341 A JPS58213341 A JP S58213341A JP 9641882 A JP9641882 A JP 9641882A JP 9641882 A JP9641882 A JP 9641882A JP S58213341 A JPS58213341 A JP S58213341A
Authority
JP
Japan
Prior art keywords
gate
output
signal
logic level
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9641882A
Other languages
English (en)
Japanese (ja)
Other versions
JPS648857B2 (enrdf_load_stackoverflow
Inventor
Masaru Uya
宇屋 優
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9641882A priority Critical patent/JPS58213341A/ja
Publication of JPS58213341A publication Critical patent/JPS58213341A/ja
Publication of JPS648857B2 publication Critical patent/JPS648857B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3876Alternation of true and inverted stages

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP9641882A 1982-06-04 1982-06-04 加算回路 Granted JPS58213341A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9641882A JPS58213341A (ja) 1982-06-04 1982-06-04 加算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9641882A JPS58213341A (ja) 1982-06-04 1982-06-04 加算回路

Publications (2)

Publication Number Publication Date
JPS58213341A true JPS58213341A (ja) 1983-12-12
JPS648857B2 JPS648857B2 (enrdf_load_stackoverflow) 1989-02-15

Family

ID=14164423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9641882A Granted JPS58213341A (ja) 1982-06-04 1982-06-04 加算回路

Country Status (1)

Country Link
JP (1) JPS58213341A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170636A (ja) * 1984-09-10 1986-04-11 レイセオン カンパニ− 全加算器回路
JPS6242230A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd スタテイツクキヤリ−回路
JPH07261983A (ja) * 1994-01-28 1995-10-13 Goldstar Electron Co Ltd 算術論理演算回路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0725630U (ja) * 1992-07-20 1995-05-12 有限会社キャプテン 遊技機械取付卓上発信機

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170636A (ja) * 1984-09-10 1986-04-11 レイセオン カンパニ− 全加算器回路
JPS6242230A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd スタテイツクキヤリ−回路
JPH07261983A (ja) * 1994-01-28 1995-10-13 Goldstar Electron Co Ltd 算術論理演算回路

Also Published As

Publication number Publication date
JPS648857B2 (enrdf_load_stackoverflow) 1989-02-15

Similar Documents

Publication Publication Date Title
US4523292A (en) Complementary FET ripple carry binary adder circuit
US3932734A (en) Binary parallel adder employing high speed gating circuitry
JPH0552529B2 (enrdf_load_stackoverflow)
JPS59139447A (ja) 全加算器
JPS595349A (ja) 加算器
US4689763A (en) CMOS full adder circuit
US4709346A (en) CMOS subtractor
JPS60116034A (ja) 加算回路
JPS58213341A (ja) 加算回路
US4905179A (en) CMOS cell for logic operations with fast carry
US4860242A (en) Precharge-type carry chained adder circuit
US4970677A (en) Full adder circuit with improved carry and sum logic gates
WO2004104820A2 (en) A sum bit generation circuit
EP0647030A2 (en) Integrated circuit devices
JPH0476133B2 (enrdf_load_stackoverflow)
JPH01228023A (ja) 全加算器
JP2849346B2 (ja) 算術論理演算回路
US5847983A (en) Full subtracter
JP3137629B2 (ja) 桁上げ‐セーブ算術演算機構に対する加算器セル
US4449197A (en) One-bit full adder circuit
JPS62293824A (ja) ゲ−ト回路
JPS648858B2 (enrdf_load_stackoverflow)
KR890001225B1 (ko) 고속 익스클루시브 오아게이트를 이용한 시모오스 가산기
JPH04117815A (ja) プログラマブル論理回路
JPH0142431B2 (enrdf_load_stackoverflow)