JPS58212136A - Forming method for ultrafine pattern - Google Patents

Forming method for ultrafine pattern

Info

Publication number
JPS58212136A
JPS58212136A JP9407882A JP9407882A JPS58212136A JP S58212136 A JPS58212136 A JP S58212136A JP 9407882 A JP9407882 A JP 9407882A JP 9407882 A JP9407882 A JP 9407882A JP S58212136 A JPS58212136 A JP S58212136A
Authority
JP
Japan
Prior art keywords
film
carbon
mask
resist
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9407882A
Other languages
Japanese (ja)
Inventor
Katsuya Okumura
勝弥 奥村
Yasuharu Suzuki
鈴木 靖治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9407882A priority Critical patent/JPS58212136A/en
Publication of JPS58212136A publication Critical patent/JPS58212136A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to form an ultrafine pattern of high quality without producing accumulation by reactively ion etching a thin carbon film as a mask. CONSTITUTION:The end of a carbon rod 10a is lightly pressed on a carbon rod 10b, energized, discharged, carbon is evaporated from a contact unit 10c, and l213F32 Si film 3 and a carbon film 11 are covered in a thickness of approx. 1,000Angstrom . Then, a resist film 12 is exposed and developed on a carbon film 11, thereby forming a resist film 12' of the prescribed pattern. With the film 12' as a mask the film 11 is reactively ion etched with O2 gas. Then, a resist removing solution such as that in which benzene sulfonic acid is mainly contained, and the resist film is removed. At this time, the film 11' remains. With the film 11' as a mask the film 3 is reactively ion etched with CCl4 and Cl2 gas, thereby forming an patterned Al.Si film 3''. Since the carbon film of this mask is sufficiently thin, side wall accumulation is not produced. Then, the carbon film is ashed with O2 plasma and removed. In this case, the Al.Si film and the SiO2 as the base of the Al.Si film are not entirely etched at all.

Description

【発明の詳細な説明】 〔発明の技術分野〕 との発明は微細パターンの形成方法にかかり、特に半導
体素子の製造における微細パターンの形成方法の改良に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The invention relates to a method for forming a fine pattern, and more particularly to an improvement in a method for forming a fine pattern in the manufacture of semiconductor devices.

(発明の技術的背景〕 薄膜を微細パターンに加工する手段として反応性イオン
エツチング法が広(用いられるようになった。反応性イ
オンエツチングは反応性のイオンビームを被エツチング
膜に垂mK照射させ、化学反応とスパッタリング現象と
を併用させてエツチングを行なわせるものである。この
とき、マスクとなっているレジスト膜の側面に被エツチ
ング物またはこの反応物が堆積してしまうことがあり、
仁の堆積物がレジスト除去1楊で完全に除去しきれない
ことがある。以下にこの問題が最も顕著であるアルミニ
ウム膜について述べる。
(Technical background of the invention) Reactive ion etching has become widely used as a means of processing thin films into fine patterns.Reactive ion etching involves irradiating a film to be etched with a reactive ion beam at mK. Etching is performed by using a combination of chemical reaction and sputtering phenomenon. At this time, the material to be etched or the reactant may accumulate on the side surface of the resist film that serves as a mask.
The deposits may not be completely removed by one resist removal process. The aluminum film in which this problem is most noticeable will be described below.

半導体素子の製造過程の一部を示す第1図ないし第4図
に右いて、(1)はシリコン基板、(21ti前記シリ
コン基板の1主面に形成された8i0.膜、(3)は前
記5iOJK被着された膜厚lpm OA! −8i膜
、(4)は前記kl−8i膜に積層して被着された膜厚
1μmのフォトレジスト膜(以下レジスト膜と略称)(
第1図)で、上記レジスト膜(4)Kパターニングを施
して所定パターンのレジスト膜(4つに形成したのちC
C/4  とCt、の混合ガスプラズマでA18i合金
膜に反応性イオンエツチングを施す(第2図)。
1 to 4 showing a part of the manufacturing process of a semiconductor device, (1) is a silicon substrate, (21ti is an 8i0. film formed on one main surface of the silicon substrate, and (3) is the above-mentioned silicon substrate. 5i OJK deposited film thickness lpm OA!-8i film, (4) is a 1 μm thick photoresist film (hereinafter abbreviated as resist film) laminated and deposited on the kl-8i film (
(Fig. 1), the above resist film (4) K patterning is applied to the resist film (4) of a predetermined pattern (after forming into four, C
Reactive ion etching is applied to the A18i alloy film using a mixed gas plasma of C/4 and Ct (Figure 2).

叙上においてレジスト膜はポジタイプのものが用いられ
ることが多く、側面は急峻になって1)る。
In the above, a positive type resist film is often used, and the side surfaces are steep (1).

これKより上記反応性イオンエツチングの終了時には第
3図に示すようにレジスト側面には堆積層(51、(5
)が形成され、レジストを除去しても第4図に示すよう
にそのまま残留する。
From this K, when the reactive ion etching is completed, as shown in FIG.
) is formed and remains as it is as shown in FIG. 4 even if the resist is removed.

〔背景技術の問題点〕[Problems with background technology]

叙上の従来の技術による堆積層を残留すると、この上に
絶縁膜を形成する際に絶縁膜が異常成長したり、堆積層
が破損して倒れて隣接のアルミニウム配線層と短絡した
りなどする重大な問題がある。上記堆積層はアルミニウ
ムのエツチング液を用いて除去することもできるが、微
細パターンにおいて鉱パターンの精度が悪化するので適
用できない。
If the deposited layer formed by the conventional technology described above remains, the insulating film may grow abnormally when an insulating film is formed on top of it, or the deposited layer may be damaged and fall down, resulting in a short circuit with the adjacent aluminum wiring layer. There is a serious problem. The deposited layer can be removed using an aluminum etching solution, but this is not applicable because the precision of the ore pattern deteriorates in fine patterns.

〔発明の目的〕[Purpose of the invention]

この発明社上記従来の技術の問題点に鑑み半導体素子の
製造における微細パターンの改良された゛製造方法を提
供する。
In view of the problems of the prior art described above, the present invention provides an improved manufacturing method for fine patterns in the manufacturing of semiconductor devices.

〔発明の概要〕 この発明にかかる微細パターンの形成方法は、マスクに
よって被膜にエツチングを施し微細パターンを形成する
方法において、マスク材にカーボン薄膜を用い反応性イ
オンエツチングによってエツチングを施すことを特徴と
するものである。
[Summary of the Invention] A method for forming a fine pattern according to the present invention is a method for forming a fine pattern by etching a film using a mask, and is characterized in that a carbon thin film is used as a mask material and etching is performed by reactive ion etching. It is something to do.

〔発明の実施例〕[Embodiments of the invention]

上に述べた堆積層についてその成因を考究すると、マス
クになるべきレジスト膜の膜厚が厚いことがあげられる
。しかし、レジスト膜では膜厚を低減するとピンホール
の発生をはじめ種々の問題が発生する。そこで発明者は
レジスト膜とAl −S i膜との間に適当なマスク材
を介挿させることを案出した。そして、マスク材として
はkt −S i膜のエツチング時にはAl−8iとの
エツチング選択比が太き(、かつ、このマスク材を除去
する時に4dA/・Si膜と下地のSin、 膜と充分
大きいエツチング選択比がとれるものが望ましいとして
種々検討の結果カーボン膜が最も好適することを認めた
When considering the cause of the above-mentioned deposited layer, it can be said that the thickness of the resist film that is to be used as a mask is thick. However, when the thickness of a resist film is reduced, various problems such as the formation of pinholes occur. Therefore, the inventor devised a method of interposing a suitable mask material between the resist film and the Al--Si film. As a mask material, when etching the kt-Si film, the etching selectivity with Al-8i is large (and when removing this mask material, the etching selectivity between the Si film and the underlying Sin film is sufficiently large. As a result of various studies, it was found that a carbon film is most suitable because it is desirable to have a good etching selectivity.

以下に第5図ないし第8図によって1実施例を説明する
。まずl実施例のカーボン膜の被着は第5図に示される
ように、lyMIを尖らせた第1のカーボン棒(10a
)の、::尖端を第2のカーボン棒(tab)に軽く押
しつけつつ通電放電させる、いイ)ゆるアーク放電を施
すとき、接触部(10C)からカーボンの蒸発をみる。
One embodiment will be described below with reference to FIGS. 5 to 8. First, as shown in FIG. 5, the carbon film of Example 1 was deposited on a first carbon rod (10a
)'s tip is lightly pressed against the second carbon rod (tab) while energizing and discharging it. (a) When performing so-called arc discharge, the evaporation of carbon from the contact portion (10C) is observed.

これによりAz−8i膜(3)カーボン膜Qυを約1o
ooKの膜厚に被”着させる。
This reduces the Az-8i film (3) carbon film Qυ to about 1o.
Deposit to a film thickness of ooK.

次に、前記カーボン膜(11)上にレジスト膜醤を回転
塗布し乾燥し、露光現像し所定パターンのレジスト膜(
12’)を形成する。ついで叙上のレジスト膜(12’
)t−マスクにして反応性イオンエツチング装置でO,
ガスを用いてカーボン膜Iにエツチングを施す(第61
1Q)。なお、との隙レジスト膜もエツチングされるが
、カーボン膜はわずか100dの膜厚であるからオーバ
ーエツチングを見込んでも充分レジストはカーボン膜の
エツチングのマスクになりうる。次にレジスト除去液、
例えばベンゼンスルフォン酸を主成分とするものでレジ
スト膜を除去する。このとき、カーボン膜はレジスト除
去液では除去されない。(11’)は残されたカーボン
膜である(第7図)。ついで上記残されたカーボン膜(
11りをマスクに反応性イオンエツチングににすCCt
、とCt、ガスを用いてλ/−f9iU(3)にエツチ
ングを施しパターン化されたAl −S +膜(3“)
に形成する(−8図)。な」6、このときマスクとなっ
ているカーボン膜は冗す薄いので背景技術に見られた側
壁堆積物は発生しない。ついでカーボン膜をO,プラズ
マによって灰化(アッシング装置による)させて除去す
る。この際A/ −S i膜およびこの下地の羽へ膜は
全くエツチングされず達成された。
Next, a resist film sauce is spin coated on the carbon film (11), dried, exposed and developed to form a resist film (11) in a predetermined pattern.
12'). Next, the resist film (12'
) using a t-mask and a reactive ion etching device.
Etching the carbon film I using gas (61st step)
1Q). Incidentally, the gap resist film is also etched, but since the carbon film is only 100 d thick, even if over-etching is expected, the resist can sufficiently serve as a mask for etching the carbon film. Next, resist removal liquid,
For example, the resist film is removed using something whose main component is benzenesulfonic acid. At this time, the carbon film is not removed by the resist removal solution. (11') is the remaining carbon film (Fig. 7). Next, remove the carbon film left above (
CCt for reactive ion etching using 11 as a mask
, and Ct, patterned Al-S+ film (3") by etching λ/-f9iU (3) using gas.
(Fig.-8). 6. At this time, since the carbon film serving as a mask is thin, the side wall deposits seen in the background art do not occur. The carbon film is then removed by ashing (using an ashing device) with O and plasma. At this time, the A/-Si film and the underlying film were not etched at all.

次に示す実施例は基板表面の凹凸が甚だしい場合に有効
な方法である。これを第9図ないし第11図によって説
明する。表面に凹凸が激しい基板QυKmlの別0県Q
擾を介してAl・Si膜(2)が1μm厚に形成されて
いる。このAl −S を膜をエツチングするためにカ
ーボン膜ed41を叙上の形成手段でtoooX厚に形
成する。この際、凹凸部の側面にも充分まわりこむよう
に基板をプラネタリ運動させる。次に第1のレジスト膜
(ハ)を厚く回転塗着し上面を平坦にする。レジスト膜
を充分乾燥させたのち、第2の810.膜04を約10
00λ厚にプラズマCYD法また杖イオンブレーティン
グ法で形成する。さらに、第2のレジスト膜<351を
0.7μm厚に薄く回転塗着する。
The following embodiment is an effective method when the surface of the substrate is extremely uneven. This will be explained with reference to FIGS. 9 to 11. Another 0 prefecture Q of the substrate QυKml with severe unevenness on the surface
An Al/Si film (2) with a thickness of 1 μm is formed through the membrane. In order to etch this Al-S film, a carbon film ed41 is formed to a thickness of too thick by the above-mentioned forming means. At this time, the substrate is moved in a planetary manner so as to sufficiently wrap around the side surfaces of the uneven portions. Next, a thick first resist film (c) is applied by spinning to make the upper surface flat. After sufficiently drying the resist film, a second 810. Membrane 04 is about 10
It is formed to a thickness of 00λ using the plasma CYD method or the cane ion blating method. Furthermore, a second resist film <351 is spin-coated to a thickness of 0.7 μm.

ついで線光視像を施し、パターニングを行なってパター
ン状の菖2のレジスト膜(35つとしたのち、このレジ
スト膜(35’)をマスクにして反応性イオンエツチン
グ法で、CF、と鳩のガスプラズマを用いて第2の8i
0.膜0邊にエツチングを施す(第9図)。
Next, line-light imaging was performed and patterning was performed to form a patterned resist film (35 pieces). Using this resist film (35') as a mask, reactive ion etching was performed to remove CF and pigeon gas. Second 8i using plasma
0. Etching is applied to the zero area of the film (Figure 9).

次に第2のStO,膜Oaをマスクとして第1のレジス
ト膜(ハ)およびカーボン膜c14に反応性イオンエツ
チング法で0.プラズマを用いてエツチングを施す(第
10図)。
Next, using the second StO film Oa as a mask, the first resist film (c) and carbon film c14 are etched by reactive ion etching. Etching is performed using plasma (Fig. 10).

次に希弗酸で第1のレジスト膜(ハ)上の第2のSム0
.膜(32’)を全面エツチング除去する。モしてA/
別膜(ハ)上にカーボン膜(財)のみを残した状態で、
とのカーボン膜をマスクにして反応性イオンエツチング
法でCCt、とC/、のガスプラズマを用いてkl −
8k膜にエツチングを施す(第11図)。なお、このと
きもマスクのカーボン膜は薄いため背景技術のようなA
/ −8i膜側壁における堆積物の発生が見られなかっ
た。また、最後に残留したカーボン膜1iOxプラズマ
(アッシング装置)で灰化させ除去することは前記実施
例と変わりない。:。
Next, the second S film on the first resist film (c) is coated with dilute hydrofluoric acid.
.. The entire surface of the film (32') is removed by etching. Moshite A/
With only the carbon film (goods) remaining on the separate film (c),
Kl −
Etching is performed on the 8k film (Figure 11). In addition, since the carbon film of the mask is thin at this time, A
/-8i No deposits were observed on the side walls of the film. Furthermore, the last remaining carbon film 1iOx plasma (ashing device) is used to incinerate and remove it, which is the same as in the previous embodiment. :.

・111 この実施例によれば基板表面の凹凸が激しい場合にも嵐
好なエツチングが達成される。
・111 According to this embodiment, excellent etching can be achieved even when the substrate surface has severe irregularities.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、カーボンの薄膜をマスクとして反応
性イオンエツチングにより微細パターンを形成し、かつ
そのエツチングの際、背景技術に見られる堆積物を生じ
ないため、能率よく高い品質の微細パターンの形成が達
成できる顕著な利点がある。
According to this invention, fine patterns are formed by reactive ion etching using a carbon thin film as a mask, and deposits seen in the background art are not generated during etching, so that fine patterns of high quality can be formed efficiently. There are significant benefits that can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第4図社従来の微細パターンの形成方法の
一部を工程順に示すいずれも断面図、第5図ないし第8
図はl実施例を工程順に示すいずれも断面図、第9図な
いし第11図は別の1実施例を工程順に示すいずれも断
面図である。 1.21      シリコン基板 2 、22     8 I Ox膜 3.23     kl−81膜 3’、 3”      パターン化されたA/−83
膜11.24      カー−ボン膜 :::≧。 11’、 24’      残゛さ、れたカーボン膜
12       レジスト膜 12’       所定パターンのレジスト膜n  
   第1の別0.膜 32      館2の81へ膜 5      第1のレジスト膜 あ      第2のレジスト膜 10B      第1のカーボン棒 Job      第2のカーボン棒 ioc       カーボン棒の接触部代理人 弁理
士   井  上  −男14 第  1 図 第2図 13図 第  4 図 115図 16図 117  図 第  8 図 319図 第10図
Figures 1 to 4 show a part of the conventional method for forming fine patterns in the order of steps, and Figures 5 to 8 are cross-sectional views.
The figures are sectional views showing one embodiment in the order of steps, and FIGS. 9 to 11 are sectional views showing another embodiment in the order of steps. 1.21 Silicon substrate 2, 22 8 I Ox film 3.23 kl-81 film 3', 3'' patterned A/-83
Film 11.24 Carbon film:::≧. 11', 24' Remaining carbon film 12 Resist film 12' Predetermined pattern of resist film n
1st different 0. Membrane 32 To 81 in building 2 Membrane 5 First resist film A Second resist film 10B First carbon rod Job Second carbon rod IOC Carbon rod contact part agent Patent attorney Inoue - 14 Figure 1 Figure 2 Figure 13 Figure 4 Figure 115 Figure 16 Figure 117 Figure 8 Figure 319 Figure 10

Claims (1)

【特許請求の範囲】[Claims] マスクによって被膜にエツチングを施して微細パターン
を形成する方法において、マスク材にカーボン薄膜を用
い反応性イオンエツチングによってエツチングを施す美
ことを特徴とする微細パターンの形成方法。
A method of forming a fine pattern by etching a film using a mask, which is characterized by the fact that a carbon thin film is used as a mask material and the etching is performed by reactive ion etching.
JP9407882A 1982-06-03 1982-06-03 Forming method for ultrafine pattern Pending JPS58212136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9407882A JPS58212136A (en) 1982-06-03 1982-06-03 Forming method for ultrafine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9407882A JPS58212136A (en) 1982-06-03 1982-06-03 Forming method for ultrafine pattern

Publications (1)

Publication Number Publication Date
JPS58212136A true JPS58212136A (en) 1983-12-09

Family

ID=14100448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9407882A Pending JPS58212136A (en) 1982-06-03 1982-06-03 Forming method for ultrafine pattern

Country Status (1)

Country Link
JP (1) JPS58212136A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01196828A (en) * 1988-02-01 1989-08-08 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device having carbon film formed thereon
JPH01198489A (en) * 1988-02-01 1989-08-10 Semiconductor Energy Lab Co Ltd Method for etching carbon film
DE4201661A1 (en) * 1991-01-22 1992-07-30 Toshiba Kawasaki Kk Semiconductor integrated circuit mfr. - uses a deposited carbon@ film as intermediate layer to improve the accuracy of reproducing sub-micron dimensions
US5240554A (en) * 1991-01-22 1993-08-31 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5378316A (en) * 1991-04-03 1995-01-03 Eastman Kodak Company High durability mask for dry etch processing of GaAs
US5437961A (en) * 1990-11-27 1995-08-01 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5445710A (en) * 1991-01-22 1995-08-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01196828A (en) * 1988-02-01 1989-08-08 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device having carbon film formed thereon
JPH01198489A (en) * 1988-02-01 1989-08-10 Semiconductor Energy Lab Co Ltd Method for etching carbon film
US5437961A (en) * 1990-11-27 1995-08-01 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
DE4201661A1 (en) * 1991-01-22 1992-07-30 Toshiba Kawasaki Kk Semiconductor integrated circuit mfr. - uses a deposited carbon@ film as intermediate layer to improve the accuracy of reproducing sub-micron dimensions
US5240554A (en) * 1991-01-22 1993-08-31 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5445710A (en) * 1991-01-22 1995-08-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5707487A (en) * 1991-01-22 1998-01-13 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5378316A (en) * 1991-04-03 1995-01-03 Eastman Kodak Company High durability mask for dry etch processing of GaAs

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