JPS58205268A - アドレス比較制御方式 - Google Patents
アドレス比較制御方式Info
- Publication number
- JPS58205268A JPS58205268A JP57089414A JP8941482A JPS58205268A JP S58205268 A JPS58205268 A JP S58205268A JP 57089414 A JP57089414 A JP 57089414A JP 8941482 A JP8941482 A JP 8941482A JP S58205268 A JPS58205268 A JP S58205268A
- Authority
- JP
- Japan
- Prior art keywords
- common bus
- processing unit
- central processing
- information
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bus Control (AREA)
- Memory System (AREA)
- Debugging And Monitoring (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57089414A JPS58205268A (ja) | 1982-05-26 | 1982-05-26 | アドレス比較制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57089414A JPS58205268A (ja) | 1982-05-26 | 1982-05-26 | アドレス比較制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58205268A true JPS58205268A (ja) | 1983-11-30 |
| JPH0364889B2 JPH0364889B2 (cg-RX-API-DMAC7.html) | 1991-10-08 |
Family
ID=13969984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57089414A Granted JPS58205268A (ja) | 1982-05-26 | 1982-05-26 | アドレス比較制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58205268A (cg-RX-API-DMAC7.html) |
-
1982
- 1982-05-26 JP JP57089414A patent/JPS58205268A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0364889B2 (cg-RX-API-DMAC7.html) | 1991-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4514808A (en) | Data transfer system for a data processing system provided with direct memory access units | |
| US4163280A (en) | Address management system | |
| EP0182044A2 (en) | Initialization apparatus for a data processing system with a plurality of input/output and storage controller connected to a common bus. | |
| JPS5843768B2 (ja) | 入出力処理システム用の指向コ−ド生成装置 | |
| JPH0479026B2 (cg-RX-API-DMAC7.html) | ||
| EP0182126A2 (en) | Directing storage requests during master mode operation | |
| US4393459A (en) | Status reporting with ancillary data | |
| US3287705A (en) | Computer system | |
| JPS58205268A (ja) | アドレス比較制御方式 | |
| JP3078000B2 (ja) | 情報処理装置 | |
| JPS6057091B2 (ja) | 共通メモリの記憶保護方式 | |
| JPS603049A (ja) | バスインタ−フエ−ス装置 | |
| JPS60178572A (ja) | マルチプロセツサ装置 | |
| JPH01140253A (ja) | バンクメモリ切換え制御方式 | |
| JPS59106060A (ja) | デ−タロギング方式 | |
| JPS60215272A (ja) | マルチプロセツサシステム | |
| JPS63129464A (ja) | 記憶アクセス制御装置 | |
| JPH0574110B2 (cg-RX-API-DMAC7.html) | ||
| JPS59121455A (ja) | プレフイクシング方式 | |
| JPS63158660A (ja) | マルチプロセツサバス制御方式 | |
| JPS6160147A (ja) | 処理要求監視方式 | |
| JPS58213371A (ja) | デ−タ処理システム | |
| JPH06242944A (ja) | コマンド実行回路 | |
| JPS6013502B2 (ja) | 構成制御指定方式 | |
| JPS62229452A (ja) | 周辺モジユ−ルアクセス方式 |