JPS58202643A - 通信バスル−ト制御方式 - Google Patents
通信バスル−ト制御方式Info
- Publication number
- JPS58202643A JPS58202643A JP57066873A JP6687382A JPS58202643A JP S58202643 A JPS58202643 A JP S58202643A JP 57066873 A JP57066873 A JP 57066873A JP 6687382 A JP6687382 A JP 6687382A JP S58202643 A JPS58202643 A JP S58202643A
- Authority
- JP
- Japan
- Prior art keywords
- communication
- communication bus
- bus
- processor
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Exchange Systems With Centralized Control (AREA)
- Small-Scale Networks (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57066873A JPS58202643A (ja) | 1982-04-21 | 1982-04-21 | 通信バスル−ト制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57066873A JPS58202643A (ja) | 1982-04-21 | 1982-04-21 | 通信バスル−ト制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58202643A true JPS58202643A (ja) | 1983-11-25 |
| JPH0233218B2 JPH0233218B2 (enExample) | 1990-07-26 |
Family
ID=13328415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57066873A Granted JPS58202643A (ja) | 1982-04-21 | 1982-04-21 | 通信バスル−ト制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58202643A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6126169A (ja) * | 1984-07-16 | 1986-02-05 | Nec Corp | 多重化処理装置 |
-
1982
- 1982-04-21 JP JP57066873A patent/JPS58202643A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6126169A (ja) * | 1984-07-16 | 1986-02-05 | Nec Corp | 多重化処理装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0233218B2 (enExample) | 1990-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4817037A (en) | Data processing system with overlap bus cycle operations | |
| JP2558393B2 (ja) | 多重クラスタ信号プロセッサ | |
| CA1221173A (en) | Microcomputer system with bus control means for peripheral processing devices | |
| JPH021037A (ja) | 共有母線のための分配仲裁装置および方法 | |
| JPH04346151A (ja) | データ処理装置及びファクシミリ装置 | |
| EP0183431B1 (en) | System control network for multiple processor modules | |
| JPS58202643A (ja) | 通信バスル−ト制御方式 | |
| JP2583586B2 (ja) | バス制御方法 | |
| JP2705955B2 (ja) | 並列情報処理装置 | |
| JPS61271555A (ja) | ダイレクトメモリアクセス転送方式 | |
| JPS58182737A (ja) | 情報処理装置 | |
| JP2666782B2 (ja) | 多重バス制御システム | |
| JPH06224975A (ja) | 結合したモジュールをリセットする方法及びこの方法を用いるシステム | |
| JPH0346855B2 (enExample) | ||
| JPS5985541A (ja) | コンソ−ル装置 | |
| JPS60182834A (ja) | コンピユ−タシステム | |
| JPH0381855A (ja) | データ転送装置 | |
| JPH04106651A (ja) | システムバスの制御装置 | |
| JPH07109595B2 (ja) | Lanアダプタの制御方式 | |
| JPS63203057A (ja) | フアクシミリ複数回線送信装置 | |
| JPS63263941A (ja) | 回線選択制御装置 | |
| JPH0391339A (ja) | 通信制御装置 | |
| JPH0427584B2 (enExample) | ||
| JPH04235660A (ja) | マルチプロセッサシステムの共通メモリ装置及び通信制御方法 | |
| JPS6272053A (ja) | プロセツサユニツト |