JPS58199543A - 半導体装置のパツケ−ジ - Google Patents
半導体装置のパツケ−ジInfo
- Publication number
- JPS58199543A JPS58199543A JP57082810A JP8281082A JPS58199543A JP S58199543 A JPS58199543 A JP S58199543A JP 57082810 A JP57082810 A JP 57082810A JP 8281082 A JP8281082 A JP 8281082A JP S58199543 A JPS58199543 A JP S58199543A
- Authority
- JP
- Japan
- Prior art keywords
- film
- package
- nickel
- plastic
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57082810A JPS58199543A (ja) | 1982-05-17 | 1982-05-17 | 半導体装置のパツケ−ジ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57082810A JPS58199543A (ja) | 1982-05-17 | 1982-05-17 | 半導体装置のパツケ−ジ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58199543A true JPS58199543A (ja) | 1983-11-19 |
| JPH0235467B2 JPH0235467B2 (enrdf_load_stackoverflow) | 1990-08-10 |
Family
ID=13784764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57082810A Granted JPS58199543A (ja) | 1982-05-17 | 1982-05-17 | 半導体装置のパツケ−ジ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58199543A (enrdf_load_stackoverflow) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4633573A (en) * | 1982-10-12 | 1987-01-06 | Aegis, Inc. | Microcircuit package and sealing method |
| JPS6212953U (enrdf_load_stackoverflow) * | 1985-07-09 | 1987-01-26 | ||
| JPH0260150A (ja) * | 1988-08-26 | 1990-02-28 | Semiconductor Energy Lab Co Ltd | 電子装置およびその作製方法 |
| US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
| JPWO2006100768A1 (ja) * | 2005-03-23 | 2008-08-28 | 富士通株式会社 | 半導体装置及びその製造方法 |
| JP2017034086A (ja) * | 2015-07-31 | 2017-02-09 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| JP2017168701A (ja) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | 半導体装置 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223248U (enrdf_load_stackoverflow) * | 1975-08-08 | 1977-02-18 |
-
1982
- 1982-05-17 JP JP57082810A patent/JPS58199543A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223248U (enrdf_load_stackoverflow) * | 1975-08-08 | 1977-02-18 |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4633573A (en) * | 1982-10-12 | 1987-01-06 | Aegis, Inc. | Microcircuit package and sealing method |
| JPS6212953U (enrdf_load_stackoverflow) * | 1985-07-09 | 1987-01-26 | ||
| JPH0260150A (ja) * | 1988-08-26 | 1990-02-28 | Semiconductor Energy Lab Co Ltd | 電子装置およびその作製方法 |
| US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
| JPWO2006100768A1 (ja) * | 2005-03-23 | 2008-08-28 | 富士通株式会社 | 半導体装置及びその製造方法 |
| JP2017034086A (ja) * | 2015-07-31 | 2017-02-09 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| JP2017168701A (ja) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0235467B2 (enrdf_load_stackoverflow) | 1990-08-10 |
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