CN1023165C - 电子器件的制造方法 - Google Patents

电子器件的制造方法 Download PDF

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CN1023165C
CN1023165C CN89108372A CN89108372A CN1023165C CN 1023165 C CN1023165 C CN 1023165C CN 89108372 A CN89108372 A CN 89108372A CN 89108372 A CN89108372 A CN 89108372A CN 1023165 C CN1023165 C CN 1023165C
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lead frame
plasma
electronic device
vacuum chamber
chip
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CN1041849A (zh
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山崎舜平
浦田一男
广濑直树
小山到
今任慎二
中下一寿
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Semiconductor Energy Laboratory Co Ltd
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Abstract

介绍一种改进的电子器件及其制造方法。该器件，比如说是一种其中带有引线，模压塑料封装的IC芯片。在模压工序之前，将IC芯片，连同引线结构，在高真空条件下涂覆一层氮化硅或其它电绝缘材料，以便保护IC芯片免遭通过封装的裂痕或间隙入侵的湿气的侵蚀。在IC芯片及其连带的结构表面清洗之后，用等离子CVD法很方便地实施氮化硅层的涂覆。

Description

本发明涉及一种电子器件的制造方法。
半导体集成电路是各领域广泛应用的最重要电子器件。然而，从可靠性角度来看，集成电路的问题之一是IC芯片被封装在塑模材料中之后，由湿气或其它杂质的侵入引起。比如封装件的裂痕或间隙会形成从封装件的外部到IC芯片表面的入侵路径。任何侵及IC表面的湿气，都会侵蚀构成IC芯片的半导体，并导致芯片功能失灵。
附图1是个表明如何在封装好的IC器件中造成损坏的示意图。
该结构包括装配在基片35′上的IC半导体芯片28，一个具有多个引线37的框架，通过引线，用金丝39，实现IC芯片28的端点与其电连接，以及封装IC芯片和引线框架的环氧树脂模压材料41。基片和/或引线框架的表面往往会氧化，形成低价氧化膜，而湿气势必会聚在这些层与封装件间的界面附近。当IC器件被组装到电路板上，实施焊接时，IC器件要经受了3～10秒钟的熔融焊料的260℃温度，因而，IC要承受一个急速的温度变化，这往往导致封装件上出现裂痕，如标号33、33′、33″。任何凝聚于封装件内的湿气将会蒸发，由蒸汽压力膨成空腔42，导致如41′所示的隆起，引起裂痕33′。这种隆起是非常可能出现的，因为氧化膜减弱了封装件与芯片35的粘着力。
上述可能发生的问题，当用银膏24把芯片28粘合到基片35上时尤为突出。芯片的粘合在加热到100℃～200℃下，用加压实现。在加热过程中，无用的有机气体自银膏24，特别从阴影部位24′逸出。一些逸出气体为引线框架的外表面所捕集，而削弱了封装件对框架的粘着力。
所以，本发明的目的是提供一种制造高可靠性的，避免引起已经有器件封装件中裂痕或其他路径侵入湿气、有机物或其它杂质等上述问题的电子器件的方法，至少在这些方面，与已有器件比，有所改善。
为了达到上述和其它的目的和优点，用有机粘结剂把电子器件固定于引线框架上，在封装之前，把器件保持在不高于10-2Torr的压力下，最好不高于10-5Torr，一般保持在5×10-3～1×10-8Torr。从有机粘结剂逸出又被器件和引线框架表面捕集的无用气态有机物，可在如此高的真空条件下被抽走。在一优选实施例中，附着于引线框架上的有机物，用等离子体灰化法去掉。该等离子体是把电能赋给氧化灰化剂，比如O2或N2O获得的。借助于氧化等离子体，使有机物分解成二氧化碳和水。在灰化之后，用清洗剂，比如Ar、Ne、Kr、H2N2或NH3进行清洗，去掉氧。最好用Ar因为Ar易转变为等离子体。灰化和清洗过程均可在5×10-1～1×10-3Torr压力下进行，最好在1×10-1～5×10-3Torr下进行。在灰化和清洗之后，可淀积一层厚度为300～500
Figure 891083723_IMG2
的保护膜，如氮化硅膜。
下面结合附图详细描述，可更好地了解本发明。
图1是说明已有器件缺点的剖面示意图。
图2是说明实际用于本发明的等离子体CVD设备的原理图。
图3A是表明支承12单元IC器件的引线框架结构平面示意图;图3B是表明图3A所示的12单元引线框架其中之一单元的放大示意图;图3C是说明如何把各个引线框架夹持在夹具中的原理图。
图4是表明依本发明的IC器件的部分剖面图。
图5A～5C是表示在发明的IC器件中，Si、N、C和O的纵深分布曲线图。
现在参照图2以及图3A～3C，下面将介绍依本发明的一个实施例的等离子体工艺方法。图2是表明等离子体CVD设备的原理剖面图。该设备包括一个淀积室1，一个通向阀门9与淀积室1相联的装卸室1′，一对设置于淀积室1内的网格或栅格电极11和11′，一个气体进给系统5，一个包括涡轮分子泵20和回转泵23，通过阀21与淀积室1相联的真空系统，一个通过匹配器25-1给电极11馈送电能的高频功率源10-1，以及一个通过匹配器25-2′给电极11′馈送电能的高频功率源10-2。功率源10-1和10-2间的相位差可用调相器26控制在180°±30°或0°±30°。气体进给系统包括五组流速计和阀门8。馈给电极11和11′的高频能量引起两极之间的阳极区辉光放电，辉光放电区（淀积区）由一个四边形的的框架40限定，以避免在区域外有不希望有的淀积。框架40由一支架40′支撑，它可以是一个接地金属框架，或是一个绝缘框架。在淀积区之内，若干IC芯片托架2由框架40支撑着，相互平行放置，间距为2～13cm，如6cm。多个IC芯片安放在各托架2上。
芯片托架由用来支撑插在两相邻的夹持装置44之间（并由其支撑）的引线框架29的夹持装置44构成，如图3A～3C所示。IC芯片用银膏粘接到由引线框架29组成的数个单元的适当部位（中心基片），并用金丝39与安置在周围的引线框架的引线端35作电连接。银膏由银粉和承载粉末的有机溶剂组成。图3B表示引线框架29的一个单元，并可看出，每个单元都设有由虚线41所确定的一片IC芯片封装所需要的引线;图中省去了芯片封装右边的引线。这种单元结构，如图3A所示，是在上、下两横条之间，沿引线框架29的长度方向重复的。一个引线框架29可以包括5～25单元结构，例如图3A的引线框架含有12单元。若干个夹持装置44可组装在一起，以承托其间10～50个如图3C所示的引线框架29，引线框29被承托在夹持装置44的凹槽内;另一种办法，是用支杆在孔51（未示出）处，把引线框架29悬挂在夹持装置上。
下面将解释涂覆于IC芯片上的保护膜措施。首先，在完成芯片与引线框架的相应的引线的电连接之后，将若干引线框架安放在托架2上，然后，通过装卸室7把托架彼此按等间隔送入淀积室。
在实际淀积保护膜之前，清洗IC器件的外表面。特别是，从IC的表面除掉有机物和低价氧化膜。首先，对淀积室抽空，排走从银价膏逸出的无用气态有机物，并让托架保持在1×10-3～1×10-8Torr。最好保持在1×10-5～1×10-8Torr。然后，将N2O由气体进给系统经喷口3送进淀积 室1，充至5×10-2Torr。再用1KW，13.56MHE的输入能量把灰化气体转变成氧化等离子体，以便在淀积室1内建立起辉光放电，IC芯片的等离子灰化时间持续5～15分钟。由于这种灰化作用，清除了附在引线框架表面上的有机物。然后，将Ar气从气体进给系统，经喷口了送入淀积室1，充至0.01～1Torr。再利用1KW，13.56MHE的输入能量，把Ar气转变成Ar等离子态，以便在淀积室1内建立起辉光放电，用等离子体清洗IC芯片持续10～30分钟。通过这样的清洗，清除了包在引线框架表面上的低价氧化膜。而且，托架的表面也被清洗了。除充Ar之外，还可掺入5～30%的H2。接着把NH2，SiH6和N2分别从输入口15，16和17通过喷口3，以适当的压力漏进淀积室1，至0.01～1Torr。NH3/Si2H6/N2的输入比为1/3/5。再一个办法是，反应气体可由Si2H6和N2组成，比例为1∶5。当1KW，1～500MH2，比如13.56MH2的高频能量输给两个电极11和11′时，则发生阳极区辉光放电。结果，在芯片上，在引线上以及它们之间的连线上均淀积上一氮化硅涂层。涂层厚度可达200～2000
Figure 891083723_IMG3
。如果淀积延续10分钟，即达1000±200
Figure 891083723_IMG4
。平均淀积速率为3
Figure 891083723_IMG5
/sec。在淀积时，托架未特殊加热。
在淀积完成之后，托架2从淀积室取出，进行下步封装工序。每个托架照原样放入模压设备，用适当的压模将环氧树脂材料（410A）注入各芯片四周封装芯片，并形成芯片的外包装。从模压设备上取下托架，切断引线使之与引线框架分开，然后将露在封装外边的各引线向下弯曲，形成IC外包装的腿，将引线用酸冲洗，然后进行焊料镀覆。
依照本发明的IC芯片内，导线连接结构如图4所示。如图所示，氮化硅保护膜覆盖住安置于基片35′上的IC芯片、接点38、金丝39以及由合金制成的引线37。由于事先采取在清洗过的表面上涂覆保护膜的措施，保护芯片免遭如图1所示，通过裂痕或间隙侵入芯片封装的湿气的侵蚀，由于在淀积氮化硅膜之前已用等离子灰化，清洗了引线框架的表面，所以能确保引线框架与氮化硅膜之间机械接合的可靠性。
根据实验推断，淀积膜的IR吸收谱在864cm-1有一个表明为Si-N键的谱峰。测得绝缘膜的耐压强度在7×106V/cm以上。测得绝缘膜的电阻率为2×105Ωcm。测得膜的反射系数为2.0。使涂层经受HF腐蚀，可以判断其保护能力。腐蚀速率为3～10
Figure 891083723_IMG6
/sce，这与氮化硅涂膜通常的估计值约30
Figure 891083723_IMG7
/sce相比，实际上是很小的。用这样极好的涂层1000
Figure 891083723_IMG8
（一般为300～5000A），可获得对IC的保护。
依照本发明制作的IC器件放入95℃的NaCl溶液中20小时，没有测出明显的变化。另外，对依本发明制作的IC器件进行20小时、2大气压、120℃的PCT（压力锅测试），测试后，没有发现有缺陷的IC。与现有技术的IC相比，损坏率从50～100FIT（非特）降低到5～10FIT;FIT＝10-9。
在相对湿度为85%，85℃的气氛中保持1000小时之后，将依本发明的等离子体灰化，清洗和涂覆的IC器件侵入熔融的260℃的焊料中3秒钟，以便加工与电路板上电路的电连接;也无裂痕，无隆起出现。
在各种各样的条件下，制备了300个样品。将这些样品置于相对湿度为85%，85℃的气氛中1000小时，并对其作可靠性测试。加热至260℃，经3秒钟实施可靠性测试。其结果列于表中。（表见文后）
从表中可以看出，当进行灰化、清洗和淀积时，没有样品损坏（批号1～5）。即使只进行灰化和淀积，而省去清洗，在100个样品（批号6～10）中也只有3个样品被损坏。若不进行灰化，即使进行了清洗和/或淀积（批号11、12、14和15），则有许多IC器件被损坏，当进行了灰化和清洗时，即使不进行淀积，也只造成1个IC的损坏。
图5A～5C是使用SIMS（二次离子质谱仪），沿样品IC表面的纵深方向测得的分子谱线图。图中曲线51、52及53分别表示Si离子，N离子及O离子的纵深分布。区域55对应于氮化硅的厚度，区域56对应于氮化硅与其下的框架间的界面，而区域57对应于下边的框架。图5A表示第5批IC的谱线。等离子体灰化和清洗的效果很明显，事实上，从曲线50可以设定，在表面处碳原子的浓度不超过2×1020/cm3，一般不超过7×1019/cm3。还可从曲线53设定氧原子的浓度不超过2×1020/cm3。图5B表示第12批的分子纵深 分布。界面的碳原子浓度特别高，可设定为3×1020～2×1021/cm3。图5C表示第7批的纵深分布。界面上氧浓度特别高，可设定为3×1020～1×1021/cm3。氧原子已被混入氮化硅膜中，导致氮化硅膜转变成氮-氧化物。碳浓度由于灰化工艺而降低至不高于2×1020/cm3，一般为1～7×1019/cm3。
虽然，用实例一一介绍了几个实施例，但应理解，本发明不限于所介绍的特例。在不背离权利要求书限定的范围的情况下，本发明可以做出改进的变型。一些例子列举如下。
类似金刚石的碳、二氧化硅或其它绝缘材料均可淀积形成保护涂层。虽然，实施例是IC芯片，但本发明也适用于其它电子器件，诸如电阻和电容。本发明采用其他焊接方法，诸如倒装法焊接、焊料震动焊接等也是有效的。
当等离子体进一步用波长为10～15μm的IR光线或用波长短于300mm的UV光线赋能时，等离子体清洗的效果会更好。
在前述实施例中，引线框架为双列直插式。但本发明也可适用其它类型框架，如扁平型封装。
表
批 灰化 清洗 Si3N4膜 吸收的 损坏
时间    时间    厚度    水份    比率
号 （分） （分） （
Figure 891083723_IMG9
） （Wt%）
1    5    15    200    0.251    0/20
2    5    15    500    0.247    0/20
3    5    15    1000    0.245    0/20
4    15    15    500    0.246    0/20
5    15    15    2000    0.251    0/20
6    5    0    200    0.253    0/20
7    5    0    500    0.251    1/20
8    5    0    1000    0.240    0/20
9    15    0    500    0.231    1/20
10    15    0    2000    0.237    1/20
11    0    15    1000    0.234    12/20
12    0    0    2000    0.254    13/20
13    5    15    0    0.263    1/20
14    0    15    0    0.249    14/20
15    0    0    0    0.252    20/20

Claims (6)

1、一种制造电子器件的方法，包括下列步骤：
用一种包含有机材料的导电膏将电子器件装配在引线框架上，将所说器件与所说引线框架实行电连接；
将载着所说器件的所说引线框架放入真空室中；
将包括含氧气体的灰化剂引进该室中；
给所说气体提供能量并产生所说气体的等离子体，以在所说电子器件和所说引线框架的表面上进行等离子体灰化作用；
将所说电子器件移离所说真空室；以及封装所说电子器件。
2、根据权利要求1的方法，其特征在于，所说灰化剂气体包括氧气或N2O。
3、一种制造电子器件的方法，包括下列步骤：
用一种包含有机材料的导电膏将电子器件装配在引线框架上，将所说器件与所说引线框架实行电连接;
将载着所说器件的所说引线框架放入真空室中;
使用一种含氧材料的等离子体在所说器件和所说引线框架表面上进行等离子体灰化作用，以从所说表面除去不需要的有机材料;
使用一种非氧化气体的等离子体在所说表面上进行等离子体清洗，以从该表面除去氧化物;以及
以塑料封装所说器件。
4、根据权利要求3的方法，其特征在于，所说含氧材料包括氧气或N2O。
5、根据权利要求3的方法，其特征在于，所说非氧化气体包括一种选自Ar、Ne、H2和NH3组合的材料。
6、一种制造电子器件的方法，包括下列步骤：
用一种包含有机材料的导电膏将电子器件装配在引线框架上，将所说器件与所说引线框架实行电连接;
将载着所说器件的所说引线框架放入真空室中;
将包括含氧材料的反应气体引进所说真空室;
抽空所说真空室，以便除去所说导电膏的蒸气;
将能量输入至所说真空室，以便将所说反应气体转变为等离子体;
将所说器件和所说引线框架的表面曝露在所说等离子体下，使得能消除不需要的粘附在所说表面上的有机材料;
从该表面除去所说有机材料后，接着就在所说真空室中以化学汽相沉积法在所说表面上形成一层包括氮化硅或类金刚石碳的保护性薄膜;以及
用有机树脂封装所说器件。
CN89108372A 1988-10-12 1989-10-12 电子器件的制造方法 Expired - Fee Related CN1023165C (zh)

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