JPS58197755A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58197755A
JPS58197755A JP57080390A JP8039082A JPS58197755A JP S58197755 A JPS58197755 A JP S58197755A JP 57080390 A JP57080390 A JP 57080390A JP 8039082 A JP8039082 A JP 8039082A JP S58197755 A JPS58197755 A JP S58197755A
Authority
JP
Japan
Prior art keywords
metal
solder
film circuit
metal plates
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57080390A
Other languages
English (en)
Inventor
Shuichiro Aku
安久 脩一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57080390A priority Critical patent/JPS58197755A/ja
Publication of JPS58197755A publication Critical patent/JPS58197755A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 不発明は半導体装置、特に高周波帯で用いられる混成集
積回路装置に関するものであるO近年、マイクロ波半導
体素子の急速な進夛に伴ない装置の小、形化、高信頼化
を目的として、マイクル波回路t−膜歯路基板上に集積
化したマイクロ波装置が広く用いられる廉になってさた
。又、史に小形化をはかるため、膜回路基板上にパッケ
ージングされていない半導体チップに@掻装着したマイ
クロ波集積回路I装置も普及しつつある0しかしマイク
ロ妓電刀用集積回路装倉は放熱特性を良好にしなければ
ならないが、その場合逆にマイクロ波特性が息くなるた
め普及が庫れている◎従来、マイクロ波電力用半導体チ
ップを直接線回路基板に装着したマイクロ波電力用集積
回w!I装置は纂1図に示すものがほとんどである。す
なわち−電体基板lの上に形成された711i!11路
40上に放熱良好な金Jlli&6を設けその上に高周
波電力用半導体素子7がA u −S bAi)のソル
ダーで半田付され、この高周波電力用半導体素子7は入
力用膜回路5及び出力用腺回路3に夫々Au@等の配線
用金all線8.9を用いて接続される□更に前記紡電
体基板1はPb−8n等のソルダにより放熱板lに半田
付される。
しかしこの様な構成のものは放熱を2!慮した金属板6
の故に、図からも明らかな碌に配線用金稿@B 、 9
の長さが長くなり、その部分に大きな自己インダクタン
スを有することになプ高周波特性を劣化させるという欠
点が生じていた。
本発明の目的は放熱特性を層化させることなく素子特性
を向上せしめた半導体装置tlI供することにある。
本発明は半導体素子の電極から引禽出される配縁用金編
線が接続されるjII[gl路の部分を半導体素子の高
さとlWI程直に高くしたことt%敵とする@以下図面
を用いて本発明の一実施例につき詳細に説明する◎ 第2図は本賽施例の蚤部断面呻である。
アル宿す等の誘電体基板1′の上に形成された膜回路4
′の上に放熱良好な金属板6′及び高周波電力用半導体
素子7′がAu−5b等のソルダで半田付され工いる@
又、入力用層回路5′及び出力用膜回路3′の上にはA
u−8n等のソルダによn5ty記半導体素子7′の上
&面とほぼ同1M1tの高さになるように金属板lO及
び11が半田付される。この金属板10.11は少なく
とも金線〇’e9’が接続される部分にのみ設けておけ
ばよい0高崗波電力用半導体素子7と前記金属板10及
び11とは金418′及び9′によシ熱圧IN郷の方法
で配−される。そして前記誘電体基板1′はPb−8n
等のソルダにより放熱板2′に半田付される。
上記の*aな説明より明らかな轍に本構造によれば配線
用金属fi18’及び9′は短かくてよいのでその自己
インダクタンスを非常に小さくすることかで龜高周波特
性を格段と向上させることができる。又、電力用半導体
素子7′とアル宿す等の誘電体基板の間には放熱の良好
な金属板61′が介在されている丸めに放熱も良好であ
ることは明らかである。
尚、金4110,11の高さは金属板6′と同4!度も
しくはそれより高くした方がよい。また本発明は通常の
半導体装置の容器内で、外部リードの先端に金属突起を
設けることに適用してもよい。
【図面の簡単な説明】
511図は従来の高周波電力混成集積回路の一実施例を
示す断面図、@2図は本発明による高周波電力混成集積
回路の一実施例を示す#面略図である。、 1 、 l’・・・誘電体基板、2.2’・・・放熱板
、3゜3′・・・出力用膜回路、4.4′・・・I11
回路、5.5′・・・入力用膜回路、6.6’・・・金
属板、7.7’・・・高周波電力用半導体素子、8.8
’・・・配−用金属線、9.9’・・・配−用金属−1
10,11・・・金属板O 代理人 弁虐十  内  原    晋(′λ) \ $/閉 第2 図

Claims (1)

  1. 【特許請求の範囲】 金属板上にif、fiされた半導体集子と、該半導体集
    子と導電体【用いて電気的Km絖される金属I−と、そ
    の上に設けられた他の金属板とt有し、^1f記半導体
    素子と前記他の金属板とが前記導電体によって配線され
    ていることを%黴とする半導体装置0
JP57080390A 1982-05-13 1982-05-13 半導体装置 Pending JPS58197755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57080390A JPS58197755A (ja) 1982-05-13 1982-05-13 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57080390A JPS58197755A (ja) 1982-05-13 1982-05-13 半導体装置

Publications (1)

Publication Number Publication Date
JPS58197755A true JPS58197755A (ja) 1983-11-17

Family

ID=13716955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57080390A Pending JPS58197755A (ja) 1982-05-13 1982-05-13 半導体装置

Country Status (1)

Country Link
JP (1) JPS58197755A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2389458A (en) * 2002-03-27 2003-12-10 Toshiba Kk Microwave integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2389458A (en) * 2002-03-27 2003-12-10 Toshiba Kk Microwave integrated circuit
GB2389458B (en) * 2002-03-27 2004-08-11 Toshiba Kk Microwave integrated circuit

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