JPS58195924A - Information signal processing device - Google Patents

Abstract

PURPOSE:To constitute a titled device so that an MPU (microprocessor) circuit or a DMA circuit can execute efficiently the processing of an information signal, by providing the third logical circuit for outputting a ready signal, on the MPU circuit. CONSTITUTION:When a DMA request signal DRQ is applied from an input/output circuit 6, a DMA circuit 2 outputs a holding request signal HRQ to a bus coupling circuit 12. When this signal HRQ is inputted to the bus coupling circuit 12, an FF13 is set, an output Q becomes high, and a holding inquiring signal HOLD is outputted. When an MPU circuit 1 outputs a holding approving signal HLDA in response to this signal, the FF13 is reset through an invertor 15 and an OR gate 16. As a result, an output of the FF13 becomes high, thereafter, a holding signal HLDA' is outputted through an AND gate 14 and an OR gate 17. Subsequently, the DMA circuit 2 outputs a switching signal AEN in accordance with the signals DRQ and HLDA'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information signal processing device, and more particularly, to an information signal processing device that uses a microprocessor circuit and a direct memory access circuit. Related to improvements in path coupling circuits.

In image information signal processing apparatuses such as facsimile machines, even standard machines must process an information signal amount of 2 megabits for negative images at high speed.

For processing information signals, a circuit device that combines a microprocessor (hereinafter referred to as MPU) circuit and a direct memory access (hereinafter referred to as DMA) circuit is used from the viewpoint of processing diversity and high speed.

A DMA circuit is a circuit that specializes in transferring information signals between input/output devices connected to a bus and memories or between memories, instead of an MPU circuit.
5~ compared to information signal transfer by circuit program processing
The actual machine can transfer data 10 times faster. However, since the transfer of information signals by the DMA circuit uses a common bus with the MPU circuit, the operation of the MPU circuit is put on standby during this transfer period.

Refer to the block diagram of the conventional information color code processing device in which the MPU circuit and the DMA circuit perform information signal processing using a common node as shown in Figure 41 and the timing chart of Figure #!2. This will be explained in detail.

A bus 3 (common to the MPU circuit w11 and the DMA path 2) is connected to the bus 3, and a memory 4 for program operation of the MPU, an input/output circuit 5 for the MPU, an input/output circuit 6 for the DMA, and a transfer information signal are connected to the bus 3. A memory 7 follows.The signal DRQ is DM.
DMA1! which is output from the DMA input/output circuit 6 to the DMA circuit 2 to round off the information signal transfer by AK. DM with request signal
When inputting A-route 2 butterfly DM payment request signal DRQ) (S3
It outputs a hold request signal HRQ requesting the usage right. When the MPU circuit circuit water-hold request signal HRQ is input, the hold permission signal HLDA is outputted once one section of program operation is completed. When the DMA circuit 2 detects this hold permission signal HLDA, it outputs a DMA response signal DAeK to notify the input/output circuit 6, and at the same time outputs a read timing signal of 1 or a write timing signal "Wk" and a transfer address signal to the bus 3. Input/output circuit 6
and the memory 7 execute information signal transfer processing by DMA between the memory areas. DMA1l request number D) tQ
is occurring continuously, multiple timing signals R
D/~'VR (I- generate and repeat information signal transfer.

Then, when the DMAfi request signal DRQ disappears and the information signal transfer process by DMA is completed, the bus 3ti returns to M P
U IIl! Usage rights are returned to Im l. Therefore, M
The PU circuit circuit MA circuit 2 uses the common bus 3 in a time-sharing manner, and the amount of information signals is large. There will be a shortage.

In the case of facsimile, as mentioned above, 2 megabits of information@
No. 16 is transmitted in about 20 seconds, but in the case of high-speed facsimile, 3 (b) ODMA transfer operations are required during this time.

This DMA transfer operation time occupies about 30% of the total transmission time, and therefore the program operation time of the MPU circuit 1 is reduced by that amount.

In order to reduce the program operation time of the MPUIgJ path due to the DMA transfer operation,
An information processing system No. 11N has been proposed in which independent buses are connected to the P1 circuit and the DMA circuit, respectively, so that the DMA circuit and the MPU circuit can simultaneously execute information signal processing. Figure @3 is a block diagram of this improved information signal processing device, in which an MPU program operation memory 4 and an MPU input/output circuit 5 are connected to the MPU (b) path 1 via an MPL1 circuit path 8. 1) MA large input/output circuit 6 transfer information signal memory 7 is connected to the DMA circuit 2 via a DMA circuit bus 9; MPU circuit bus 8 and DMA
The circuit buses 9 are connected to each other by a bus coupling circuit 10,
DMA-path 2 via MPU circuit 1ti input/output circuit 11
connected to control the

In this improved information signal processing device, the path coupling circuit l
By electrically disconnecting O from Kll, information signal processing of each tic can be executed simultaneously using buses 8 and 9 of MPLJ Sonoro I and L) MA Sonoro 2. M.P.
The U circuit 1 inputs the operating state original signal of the DMA (b) path 2 via the input/output circuit 11, judges it by the hzpu times MI (D7cJ gram processing (software) VC), and then outputs the DMA signal.
Controls I circuit 2. Then, MPUl0 circuit 1 is DM
When a command is given to the A Tsumugiji 2 in response to a program, it is given through the A-Tsumugiji 11, and the MPU circuit 1 uses the DMA (
b) When processing Information Ipo using bus 9, I
Give the -m stop 6h command to the JMA circuit 2, and send the DMA circuit 2 positive status (cut off) signal AEN (@2 Figure N)
I try to run it after #M is finished.

Therefore, this improved information signal processing f! ! /A device is MP
UIL! J Road l and L) MA [! ! The information signal processing ability is improved because the information signals 2 and 2 can simultaneously perform the respective information processing. However, like fax, DM
A @ work is intermittent, and the MPU (mouth) route is DMA1.
When information signal processing is frequently executed using the 1-way Hass 9, the number of commands and confirmations from the MPtJ circuit 1 to the DMA-2 and the number of program executions increases, and the MPU circuit 1 becomes unable to carry out the original program processing. It is less effective in preventing a decrease in operating time.

It is therefore an object of the present invention to provide an information processing system that allows an MPU circuit or an MA circuit to efficiently perform information signal processing.
Our objective is to provide an information signal processing device with excellent No. 6 processing ability.

Rounding this target to 4, the present invention provides a bus coupling circuit that connects the MPU circuit bus and the ML)A circuit bus with the L)MA circuit bus.
When a hold request signal is input from the circuit, NI P
an Ml logic circuit which inputs the state signal of the U circuit and outputs a hold signal to the DMA[r′I circuit; and @i+ED.
a second logic that electrically interrupts the connection means between the MPU circuit bus and the DMA circuit bus by determining the switching signal input from the M A circuit and the output signal of the address decoder connected to the MPU circuit bus; By providing a circuit and a third logic circuit that logically judges the switching signal and the output signal of the address decoder and outputs a ready signal to the MPU path, the usage right between both buses can be controlled. By processing the control in the bus coupling circuit, the MPU circuit and the DMA circuit can be operated efficiently and the information signal processing ability can be improved. Explain in detail.

FIG. 4 is a block diagram of an information signal processing device according to an embodiment of the present invention, and the difference from the improved information signal processing device described in 'js3- is that
) The bus axis combining circuits 1 and 2 that connect the MAA bus 9 are connected to the M
PUlpJwll Thanks DMA1g1M2 /1! I/4Jv#(, MPU
(口) Output the judgment result to the path 1 and the DMA circuit 2, and also check the electrical coupling between the buffs 8 and 9 IIIAtIIllI@
It's about doing. Components that are the same as those in FIG. 3 are designated by the same reference numerals and detailed explanations will be omitted.

FIG. 5 is a detailed electrical diagram of the bus coupling circuit 12. Hold approval HR output from DMA circuit 2
Qti, clock terminal CL of the free-lag flop circuit 13
K and AND gate) 14.

Output terminal QtiMP (hold inquiry signal toward J circuit 1) 10LD of flip 70 toggle path 13 is output.

Hold permission signal HLDA output from MPυ circuit l
is inverted by the inverter 15, and then the negative logic OR gate 16
The signal is applied to the reset terminal PC of the flip circuit 13 through the flip circuit 7a. The reset signal RESET output from the ordinary MPIJ circuit 1 is also applied to the reset terminal PC of the 7-lip lock circuit 13 via the OR gate 16. The signal of the output terminal Q of the 7-rig circuit 13 is input to the other input terminal of the AND gate 14, and the output signal of the AND gate 14/riOR gate 1
A hold signal H L is sent to the DMA circuit 2 via
Output as DA'. The switching number AEN inputted from the DMA circuit 2 is converted into the hold signal HLDA' via the OR gate 17, and is also converted into the negative logic A.
(ND) is input to one input terminal of 18, and further inverted by inverter 19 to generate another negative -! The output signal of the address decoder 21 connected to the MPU circuit bus 8 is input to the other input terminal of the AND gate 20 (ANDA-) 2 (1). input manually to the other input terminal. The three-state bus buffer circuit 22 that connects the MPU circuit bus 8 and the DMAtg circuit bus 9 has its connection state controlled by the output signal of the AND gate 18. Furthermore, the output signal READY to the AND gate 20 is MPUI! II! Jf
It is output as a Luday signal to MIl.

The operation of the information signal processing apparatus shown in FIGS. 4 and 5 will be explained with reference to the timing chart shown in FIG. 6.

DMAIIL request signal D from input/output circuit 6 to DMA circuit 2
)LQ is applied, the DMA (b) path 2 outputs a bold request signal IRQ to the bus coupling circuit 12. When the hold request signal IRQ is input to the bus coupling circuit 12t-11, the flip-flop circuit 13 is set and the output Q becomes high level, thereby outputting the hold request signal HOLD. MPUIgl is this hold inquiry signal HOLD
If you respond with K and output hold fraud O] polarized HLDA,
Since the output Q of the flip-flop circuit 1313 becomes high level through the inverter 15 and the OK gate 16, the A
A hold signal HL IJ A' is output through the OR gate 17 and the DMA circuit 2 outputs MDA request No. 16 IJ1tQ and a hold signal 1-I L l).
A switching signal AEN is output in response to A'. This switching signal AEN controls the bus buffer 1 path 22 via the AND gate 18 to control the MPU circuit bus 8 and DM.
A [The electrical connection of the g-route bus 9 is cut off, and the DMA circuit 2
uses the DMA circuit bus 9 to perform information signal processing. On the other hand, when the MPU circuit internal hold enable signal HLDA is output, the flip-flop circuit 13 is reset and the output Q becomes low level, so the hold inquiry signal HOLD is output.
Since the MPU circuit 11 is no longer held and the MPU circuit lFi hold is released, the MPU circuit 11 can perform signal processing that is not directly related to the tDMA operation. In addition, bus coupling circuit 1
MPU circuit bus 8 and D by bus buffer circuit 22 of 2
The electrical connection of the MA circuit bus 9 is cut off based on the hold permission signal HLDA output from the MPU path 1, so the operation of the MA circuit bus 2 (in the MPU circuit circuit) and the timing of disconnection of the bus m It will never shift.

Also, when the DMA circuit 2 is in the MPU circuit during DMA operation,
When attempting to transfer the A1g1 route bus 9 to 1st, the bus buffer circuit 22 electrically cuts off the MPU circuit bus 8 and the DMA circuit bus 9 because the high level switching signal AKN is given to the AND game 18. “It remains as it is,”
Further, since the output of the address decoder 21 becomes low level, the AND gate 20 outputs a ready signal (tEADY) within the MPU circuit, thereby setting the internal MPU circuit in the internal state.

When the DMA operation is completed, the switching signal AEN becomes low level, so the AND gate 18 satisfies the input condition and operates the bus buffer circuit 22 to electrically connect the MPU circuit bus 8 and the DMA circuit bus 9. shall be. At the same time, the input conditions of the AND gate 20 are not satisfied, so the ready signal READY is released, and the MPU circuit
In the electrical path alignment state control by the bus coupling circuit 12 described above, which makes it possible to execute pressure information signal processing using the A circuit bus 9, special consideration must be given to the program within the MPU circuit to reduce construction costs. Therefore, the operation time of the program executed for controlling the connection state can be reduced.

FIG. 7 is a circuit diagram showing a modification of the bus coupling circuit 12.
) The MA circuit 2 can start a DMA operation only when the MA (ro) bus 9 in the MPU circuit is not in use, and if the MPLj circuit l attempts to use the DMA circuit bus 9 during a DMA operation, It is designed to generate a ready signal. NAND gate 23 inputting the hold consent signal HRQ and the output signal of the address decoder 21
The output signal of j! It is input to the lOR gate 24 and inverted by the inverter 25 to generate a hold signal -jtHLD.
It is output to the DMA circuit 2 as A'. The switching signal AEN supplied from the DMA circuit 2 to one input terminal of the negative logic ANI gate 8 which controls the bus buffer circuit 22 which controls the electrical connection between the MPU circuit bus 8 and the DMA circuit bus 9 is , is inverted by the inverter 19 and inputted to the front hpi OR gate 24. Shell @ buried AND game -
A ready signal READY is outputted to the MPU circuit 20 by the output signal of the address encoder 21 and the output signal of the OH gate 24.

Accordingly, in this modification, the hold cost is obtained from the LAMA circuit 2 (when inputting the st-14 HRQ, if the MPLJ circuit l uses the DMA circuit bus 9 and -C is not present, the output signal of the address decoder 21 is)・Because I'm level-headed, N
The output signal of the ANI) gate 23 becomes low level, and the inverter 25 outputs a hold signal Q)ILDA'. As a result, the DMA circuit 2 outputs the switching signal AENI, maintains the bus connection state by the bus buffer (lower) path 22, and enters the Dfli4A operation.
Even if the MPLI direction path l attempts to use the DMA circuit bus 9 during the operation, the input conditions of AND gate 18~ are not satisfied, so the bus node (sofa circuit 22 maintains the bus connection state, and the AND gate 200A force condition is MP because it is established
A ready signal READY is output after the U circuit is completed.

Part 4) After the DMA operation is completed, the switching signal AE is activated.
When N becomes low level, the input condition of ANL) 18 is satisfied, and the bus buffer (B) path 22 electrically connects the MPU circuit bus 8 and the DMA circuit bus 9 to connect the MPU circuit bus 8 and the DMA circuit bus 9. When the MPU circuit bus 9 is in use,
) The hold request signal HRQ is output from the M A circuit 2.
However, since the output signal of the address decoder 21 is at low level, the input condition of the NAND gate 23 is not satisfied.
Therefore, the hold signal HL D A'ri is not generated and the DM
Cannot enter A action. And MP tjN road IK by D
When the use of the MA circuit bus 9 is completed, the output signal of the address decoder 21 becomes low level, the input condition of the NAND gate 23 is satisfied, and the DMA operation becomes possible as in the case described above. As in the case described above, the MPU circuitry can process its own information signal IIJI during the DMA operation.

In this modification, there is no need for program processing for each MPU circuit size to disconnect or disconnect the electrical connection between the temperature nodes, so the original information signal processing program execution time is not reduced.

As explained above, according to the present invention, the connection circuit itself logically processes the state signals of the MPU circuit and the DMA circuit to control the on/off of electrical coupling between the buses.
! 1'F, the MPU circuit can reduce program processing for (S) connection control and increase the number of original information signal processing devices, thus improving the information signal processing device of the device. Effectiveness; obtainable.

[Brief explanation of the drawing]

Figure 1 shows a conventional information signal processing device.
Figure 3 is a block diagram of the improved Friendship @ signal processing device, Figure 4 is a block diagram of the information signal processing device of the present invention, and Figure 5 is a detailed electrical diagram of the bus coupling circuit. 6 is an operation timing chart, and FIG. 7 is an electrical circuit diagram of a modified example of the node coupling circuit. l...MPU circuit, 2...DMA circuit, 4...memory for program operation, 6...DMA input/output circuit, 7
...Memory for transfer information, 8...MPU circuit no.
9...DM A IJ bus 12...Bus coupling circuit, 21...Address decoder, 22...3#?
tl) (Snow (sofa circuit, IRQ...Hold requested signal, HLI) A'...Hold signal 1, AEN...
・Switching signal, RE A D Y
MPU Fig. 3 Fig. 4 Fig. 5 Fig. 2 (Fig. 3

Claims (1)

[Scope of Claims] 1. A microprocessor circuit, a program operation memory of the microprocessor, a microprocessor path that connects the microprocessor circuit and the program operation memory, and a direct memory access ( (b) A direct memory access input/output circuit, a transfer information signal memory, a direct memory access circuit described in 1IIJ, and a direct memory access circuit T-connected to the input/output circuit and the transfer information signal memory. information signal processing comprising: a bus; and a bus coupling circuit that controls an electrical coupling state between the microprocessor circuit bus and the direct memory access circuit bus depending on the operating states of the microprocessor circuit and the direct memory access circuit. In the apparatus, the bus coupling circuit includes a first bus coupling circuit that inputs a state signal of a spinning microprocessor circuit and outputs a hold signal to the direct memory access circuit when a hold request signal is input from the direct memory access 11gl path. a logic circuit, a switching signal input from the direct memory access circuit, and the microprocessor circuit bus Km&1tE.
a set 2 logic circuit for making a logical judgment on the output signal of the address decoder and electrically cutting off the connection means between the buses; An information signal processing device comprising three logic circuits for outputting a ready signal to a microprocessor circuit. 2. In claim 1.11, the first item 1.
The 11f logic circuit has a flip-flop circuit that is set by the hold request signal and outputs a hold request signal to the microprocessor circuit, and is reset by a hold permission signal input from the microprocessor (b) circuit. #An information signal processing device that generates images. 3. An information signal processing device according to Claim 1K, wherein the first logic circuit converts the output signal of the address decoder into the form 111 (No. 1) of the microprocessor circuit. .