JPS58195250A - デイジタル加算回路 - Google Patents
デイジタル加算回路Info
- Publication number
- JPS58195250A JPS58195250A JP57077066A JP7706682A JPS58195250A JP S58195250 A JPS58195250 A JP S58195250A JP 57077066 A JP57077066 A JP 57077066A JP 7706682 A JP7706682 A JP 7706682A JP S58195250 A JPS58195250 A JP S58195250A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- input
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49942—Significance control
- G06F7/49947—Rounding
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57077066A JPS58195250A (ja) | 1982-05-08 | 1982-05-08 | デイジタル加算回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57077066A JPS58195250A (ja) | 1982-05-08 | 1982-05-08 | デイジタル加算回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58195250A true JPS58195250A (ja) | 1983-11-14 |
JPH0418334B2 JPH0418334B2 (enrdf_load_stackoverflow) | 1992-03-27 |
Family
ID=13623416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57077066A Granted JPS58195250A (ja) | 1982-05-08 | 1982-05-08 | デイジタル加算回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58195250A (enrdf_load_stackoverflow) |
-
1982
- 1982-05-08 JP JP57077066A patent/JPS58195250A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0418334B2 (enrdf_load_stackoverflow) | 1992-03-27 |
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