JPS58182242A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS58182242A
JPS58182242A JP57065021A JP6502182A JPS58182242A JP S58182242 A JPS58182242 A JP S58182242A JP 57065021 A JP57065021 A JP 57065021A JP 6502182 A JP6502182 A JP 6502182A JP S58182242 A JPS58182242 A JP S58182242A
Authority
JP
Japan
Prior art keywords
wiring
fixed
wirings
integrated circuit
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57065021A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0434309B2 (enrdf_load_stackoverflow
Inventor
Suketaka Yamada
山田　資隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57065021A priority Critical patent/JPS58182242A/ja
Publication of JPS58182242A publication Critical patent/JPS58182242A/ja
Publication of JPH0434309B2 publication Critical patent/JPH0434309B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP57065021A 1982-04-19 1982-04-19 半導体集積回路装置 Granted JPS58182242A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57065021A JPS58182242A (ja) 1982-04-19 1982-04-19 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57065021A JPS58182242A (ja) 1982-04-19 1982-04-19 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS58182242A true JPS58182242A (ja) 1983-10-25
JPH0434309B2 JPH0434309B2 (enrdf_load_stackoverflow) 1992-06-05

Family

ID=13274898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57065021A Granted JPS58182242A (ja) 1982-04-19 1982-04-19 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS58182242A (enrdf_load_stackoverflow)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110137A (ja) * 1983-11-18 1985-06-15 Sanyo Electric Co Ltd 半導体装置
US4910574A (en) * 1987-04-30 1990-03-20 Ibm Corporation Porous circuit macro for semiconductor integrated circuits
JP2012124510A (ja) * 2007-08-02 2012-06-28 Tela Innovations Inc 集積回路デバイス
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9704845B2 (en) 2010-11-12 2017-07-11 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US9779200B2 (en) 2008-03-27 2017-10-03 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US10446536B2 (en) 2009-05-06 2019-10-15 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621364A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621364A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor integrated circuit

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110137A (ja) * 1983-11-18 1985-06-15 Sanyo Electric Co Ltd 半導体装置
US4910574A (en) * 1987-04-30 1990-03-20 Ibm Corporation Porous circuit macro for semiconductor integrated circuits
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US10186523B2 (en) 2006-03-09 2019-01-22 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
US10230377B2 (en) 2006-03-09 2019-03-12 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US10217763B2 (en) 2006-03-09 2019-02-26 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
US10141335B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
US9859277B2 (en) 2006-03-09 2018-01-02 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US10141334B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US10074640B2 (en) 2007-03-05 2018-09-11 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
JP2012124510A (ja) * 2007-08-02 2012-06-28 Tela Innovations Inc 集積回路デバイス
US10734383B2 (en) 2007-10-26 2020-08-04 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US10461081B2 (en) 2007-12-13 2019-10-29 Tel Innovations, Inc. Super-self-aligned contacts and method for making the same
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US10651200B2 (en) 2008-03-13 2020-05-12 Tela Innovations, Inc. Cross-coupled transistor circuit defined on three gate electrode tracks
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US9871056B2 (en) 2008-03-13 2018-01-16 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US10020321B2 (en) 2008-03-13 2018-07-10 Tela Innovations, Inc. Cross-coupled transistor circuit defined on two gate electrode tracks
US10658385B2 (en) 2008-03-13 2020-05-19 Tela Innovations, Inc. Cross-coupled transistor circuit defined on four gate electrode tracks
US10727252B2 (en) 2008-03-13 2020-07-28 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US9779200B2 (en) 2008-03-27 2017-10-03 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US10446536B2 (en) 2009-05-06 2019-10-15 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9704845B2 (en) 2010-11-12 2017-07-11 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

Also Published As

Publication number Publication date
JPH0434309B2 (enrdf_load_stackoverflow) 1992-06-05

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