JPH0434309B2 - - Google Patents

Info

Publication number
JPH0434309B2
JPH0434309B2 JP57065021A JP6502182A JPH0434309B2 JP H0434309 B2 JPH0434309 B2 JP H0434309B2 JP 57065021 A JP57065021 A JP 57065021A JP 6502182 A JP6502182 A JP 6502182A JP H0434309 B2 JPH0434309 B2 JP H0434309B2
Authority
JP
Japan
Prior art keywords
wiring
basic cells
gate electrode
fixed
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57065021A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58182242A (ja
Inventor
Suketaka Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57065021A priority Critical patent/JPS58182242A/ja
Publication of JPS58182242A publication Critical patent/JPS58182242A/ja
Publication of JPH0434309B2 publication Critical patent/JPH0434309B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP57065021A 1982-04-19 1982-04-19 半導体集積回路装置 Granted JPS58182242A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57065021A JPS58182242A (ja) 1982-04-19 1982-04-19 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57065021A JPS58182242A (ja) 1982-04-19 1982-04-19 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS58182242A JPS58182242A (ja) 1983-10-25
JPH0434309B2 true JPH0434309B2 (enrdf_load_stackoverflow) 1992-06-05

Family

ID=13274898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57065021A Granted JPS58182242A (ja) 1982-04-19 1982-04-19 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS58182242A (enrdf_load_stackoverflow)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110137A (ja) * 1983-11-18 1985-06-15 Sanyo Electric Co Ltd 半導体装置
US4910574A (en) * 1987-04-30 1990-03-20 Ibm Corporation Porous circuit macro for semiconductor integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7908578B2 (en) * 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101761530B1 (ko) 2008-07-16 2017-07-25 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843905B2 (ja) * 1979-07-31 1983-09-29 富士通株式会社 半導体集積回路の製造方法

Also Published As

Publication number Publication date
JPS58182242A (ja) 1983-10-25

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