JPS58170847U - Structure of hybrid integrated circuit with heat dissipation fins - Google Patents

Structure of hybrid integrated circuit with heat dissipation fins

Info

Publication number
JPS58170847U
JPS58170847U JP1982066777U JP6677782U JPS58170847U JP S58170847 U JPS58170847 U JP S58170847U JP 1982066777 U JP1982066777 U JP 1982066777U JP 6677782 U JP6677782 U JP 6677782U JP S58170847 U JPS58170847 U JP S58170847U
Authority
JP
Japan
Prior art keywords
heat dissipation
dissipation fins
integrated circuit
board
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982066777U
Other languages
Japanese (ja)
Other versions
JPS638142Y2 (en
Inventor
小崎　良一
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1982066777U priority Critical patent/JPS58170847U/en
Publication of JPS58170847U publication Critical patent/JPS58170847U/en
Application granted granted Critical
Publication of JPS638142Y2 publication Critical patent/JPS638142Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の放熱フィン付き混成集積回路の構造を示
す正面図、第２図乃至第４図は本考案に係る放熱フィン
付き混成集積回路の実施例を示すもので、第２図は全体
概要を示す正面図、第３図は基板に対するリード接続、
固定用導体パターン形成要領を示す斜視図、第４図はセ
ラミックケースに対するリード固定用導体形成要領を示
す斜視図である。 図中、１１は基板、１２Ａ、１２Ｂは実装部品、１３は
セラミックケース、１４は放熱フィン、１５はリード、
１６はリードの基部、１７はり−ド嵌合用凹部、１８は
端子接続、固定用導体パターン、１９．２０は半田、２
１はリード固定用導体である。Fig. 1 is a front view showing the structure of a conventional hybrid integrated circuit with heat dissipation fins, and Figs. 2 to 4 show examples of the hybrid integrated circuit with heat dissipation fins according to the present invention. Front view showing the outline, Figure 3 shows the lead connection to the board,
FIG. 4 is a perspective view showing how to form a fixing conductor pattern. FIG. 4 is a perspective view showing how to form a lead fixing conductor to a ceramic case. In the figure, 11 is a board, 12A and 12B are mounted components, 13 is a ceramic case, 14 is a radiation fin, 15 is a lead,
16 is the base of the lead, 17 is a recess for fitting the beam, 18 is a conductor pattern for terminal connection and fixing, 19.20 is solder, 2
1 is a lead fixing conductor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 表面に電気部品を搭載した基板と、前記基板の表面に前
記電気部品を覆って取り付けられたセラミックケースと
、前記基板の裏面に取り付けられた放熱フィンと、一端
が前記基板の裏面に接続、固定されて引き出される複数
のリードとを備えた放熱フィン付き混成集積回路におい
て、前記セラミックケースをほぼ前記基板１杯の大きさ
とし、前記リードを前記基板、前記セラミックケースを
はさみ込んで引き出すとともに、前記リードを前記セラ
ミックケースの表面に半田付けにより固定したことを特
徴とする放熱フィン付き混成集積口・　路の構造。−A board with electrical components mounted on its surface; a ceramic case attached to the surface of the board to cover the electrical components; a heat dissipation fin attached to the back surface of the board; one end connected and fixed to the back surface of the board. In the hybrid integrated circuit with heat dissipation fins, the ceramic case is approximately the same size as the substrate, the leads are sandwiched between the substrate and the ceramic case, and the leads are pulled out. A hybrid accumulation opening/channel structure with heat dissipation fins is fixed to the surface of the ceramic case by soldering. −
JP1982066777U 1982-05-08 1982-05-08 Structure of hybrid integrated circuit with heat dissipation fins Granted JPS58170847U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982066777U JPS58170847U (en) 1982-05-08 1982-05-08 Structure of hybrid integrated circuit with heat dissipation fins

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982066777U JPS58170847U (en) 1982-05-08 1982-05-08 Structure of hybrid integrated circuit with heat dissipation fins

Publications (2)

Publication Number Publication Date
JPS58170847U true JPS58170847U (en) 1983-11-15
JPS638142Y2 JPS638142Y2 (en) 1988-03-10

Family

ID=30076629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982066777U Granted JPS58170847U (en) 1982-05-08 1982-05-08 Structure of hybrid integrated circuit with heat dissipation fins

Country Status (1)

Country Link
JP (1) JPS58170847U (en)

Also Published As

Publication number Publication date
JPS638142Y2 (en) 1988-03-10

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