JPS58170843U - Packages for integrated circuits - Google Patents

Packages for integrated circuits

Info

Publication number
JPS58170843U
JPS58170843U JP6659482U JP6659482U JPS58170843U JP S58170843 U JPS58170843 U JP S58170843U JP 6659482 U JP6659482 U JP 6659482U JP 6659482 U JP6659482 U JP 6659482U JP S58170843 U JPS58170843 U JP S58170843U
Authority
JP
Japan
Prior art keywords
packages
integrated circuits
integrated circuit
circuit package
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6659482U
Other languages
Japanese (ja)
Inventor
豊 米田
原川　孝夫
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP6659482U priority Critical patent/JPS58170843U/en
Publication of JPS58170843U publication Critical patent/JPS58170843U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structure Of Printed Boards (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来技術によるセラミック基板とその上に形成
された導電パターンを示す図、第一１図は本考案はぼよ
る集積回路用パッケージのセラミック基板とその上に形
成された導電パターンを示す図である。FIG. 1 shows a ceramic substrate and a conductive pattern formed on it according to the prior art, and FIG. 11 shows a ceramic substrate and a conductive pattern formed on it for an integrated circuit package according to the present invention. It is a diagram.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路用パッケージにおいて、信号用ピンの信号経路
の周辺にシールドパターンを形成したこと番特徴とする
集積回路用パッケージ。An integrated circuit package characterized in that a shield pattern is formed around the signal path of the signal pin.
JP6659482U 1982-05-10 1982-05-10 Packages for integrated circuits Pending JPS58170843U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6659482U JPS58170843U (en) 1982-05-10 1982-05-10 Packages for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6659482U JPS58170843U (en) 1982-05-10 1982-05-10 Packages for integrated circuits

Publications (1)

Publication Number Publication Date
JPS58170843U true JPS58170843U (en) 1983-11-15

Family

ID=30076458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6659482U Pending JPS58170843U (en) 1982-05-10 1982-05-10 Packages for integrated circuits

Country Status (1)

Country Link
JP (1) JPS58170843U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587462A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Integrated circuit package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587462A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Integrated circuit package

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