JPS58161344A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58161344A
JPS58161344A JP4279782A JP4279782A JPS58161344A JP S58161344 A JPS58161344 A JP S58161344A JP 4279782 A JP4279782 A JP 4279782A JP 4279782 A JP4279782 A JP 4279782A JP S58161344 A JPS58161344 A JP S58161344A
Authority
JP
Japan
Prior art keywords
film
silicon
molybdenum
point metal
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4279782A
Other languages
Japanese (ja)
Other versions
JPH041497B2 (en
Inventor
Hiroshi Norimoto
寛 法元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4279782A priority Critical patent/JPS58161344A/en
Publication of JPS58161344A publication Critical patent/JPS58161344A/en
Publication of JPH041497B2 publication Critical patent/JPH041497B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To silicify a high melting-point metal in a section being in contact with silicon, and to simplify processes by forming a silicon thin-film onto an insulating film, coating the silicon thin-film with the high melting-point metal and thermally treating the whole in an oxygen atmosphere. CONSTITUTION:A silicon oxide film 22 is formed onto a silicon substrate 21 through a thermal oxidation method, and a polysilicon film 23 is formed onto the oxide film through a CVD method, and patterned through a photolithography process. A molybdenum film 24 is formed onto the polysilicon film 23 through magnetron sputtering, and thermally treated in the oxygen atmosphere, and a molybdenum silicide is formed.

Description

【発明の詳細な説明】 この発明は、高融点金属を用いて低抵抗の電極配線を形
成するようにした半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which low-resistance electrode wiring is formed using a high-melting point metal.

従来、半導体装置、特に、半導体集積回路において、電
極および内部配線材料として、ポリシリコンを用いる構
造が広く用いられているが、微細化、高集積化が進むに
つれて、配線抵抗の低下への要求が大きくなシ、ポリシ
リコンよりも抵抗の小さい高融点金属または高融点金属
とシリコンとの化合物(以下、金属シリサイドと云う)
が電極材料として用いられてきた。中でも、モリブデン
シリサイドがよく用いられておシ、その形成方法の一例
を第1図fa)〜第1図(d+により説明する。
Conventionally, structures using polysilicon as electrodes and internal wiring materials have been widely used in semiconductor devices, especially semiconductor integrated circuits, but as miniaturization and higher integration progress, there is a demand for lower wiring resistance. A high-melting point metal or a compound of a high-melting point metal and silicon (hereinafter referred to as metal silicide), which has a larger resistance than polysilicon.
has been used as an electrode material. Among these, molybdenum silicide is often used, and an example of its formation method will be explained with reference to FIGS. 1fa) to 1(d+).

まず、第1図fa)に示すように、シリコン基板11上
にr−)絶縁膜12を被着して、その上にポリシリコン
膜13を被着し、さらに、その上にモリブデン膜14を
被着する。
First, as shown in FIG. to adhere to.

次に、これを窒素基囲気中で約600℃の熱処理を行い
、モリブデン膜14とポリシリコン膜13を反応させ、
第1図(b)に示すように、モリブデンシリサイド膜1
5を形成する。このとき、ポリシリコン膜13が十分厚
く、熱処理時間が十分に長いと、モリブデン膜14がす
べて、シリサイド化し、ポリシリコン膜13が一部残る
Next, this is heat-treated at about 600° C. in a nitrogen-based atmosphere to cause the molybdenum film 14 and polysilicon film 13 to react,
As shown in FIG. 1(b), a molybdenum silicide film 1
form 5. At this time, if the polysilicon film 13 is sufficiently thick and the heat treatment time is sufficiently long, all of the molybdenum film 14 is turned into silicide, and a portion of the polysilicon film 13 remains.

まだ、モリブデンシリサイド膜15の表面に雰囲気中の
残留酸素とポリシリコン膜13から波数してきたシリコ
ンが反応して薄いシリコン酸化膜16が形成される。
A thin silicon oxide film 16 is still formed on the surface of the molybdenum silicide film 15 due to the reaction between the residual oxygen in the atmosphere and the silicon that has come from the polysilicon film 13 .

次に、第1図[e)に示すように、シリコン酸化膜16
上にホトレジストパターン17を形成する。
Next, as shown in FIG. 1[e], the silicon oxide film 16
A photoresist pattern 17 is formed thereon.

これを四フッ化炭素と酸素の混合ガスによシプラズマエ
ッチングを行うと、第1図Cd)に示すように、モリブ
デンシリサイド膜15上のシリコン酸化膜16がモリブ
デンシリサイド膜15よシエッチング速度が小さいため
に、シリコン酸化膜16にひさし状の突起18が形成さ
れることがある。
When this is subjected to plasma etching using a mixed gas of carbon tetrafluoride and oxygen, as shown in FIG. Because of the small size, an eave-like protrusion 18 may be formed on the silicon oxide film 16.

このような突起18が存在すると、この上に薄膜を形成
するときに十分に該層されず、一部下地が露出するなど
の問題が生じる。
If such a protrusion 18 exists, a problem arises in that when a thin film is formed on the protrusion 18, the layer is not sufficiently coated and a portion of the underlying layer is exposed.

また、一般にモリブデン膜14とモリブデンシリサイド
膜15とでは、エツチング速度が異なるため、モリブデ
ンシリサイド膜15とポリシリコン膜13との界面でバ
タンエツジが歪曲することがあり、歪19が形成される
。この場合も、この上に形成する薄膜の被接を劣化させ
るなどの問題が生じる。
Furthermore, since the etching rates of the molybdenum film 14 and the molybdenum silicide film 15 are generally different, the batten edge may be distorted at the interface between the molybdenum silicide film 15 and the polysilicon film 13, resulting in distortion 19. In this case as well, problems such as deterioration of the adhesion of the thin film formed thereon arise.

これらの問題はこのような方法で形成したモリブデンシ
リサイド膜が多層構造になると云う点およびそれぞれの
膜のエツチング特性が一般に異なると云う点に由来して
いる5 これらの問題に対しては、それぞれの膜を個別にエツチ
ングするなどの方法で対処できるが、その場合、工程が
複雑になる。
These problems stem from the fact that the molybdenum silicide film formed by this method has a multilayer structure and that the etching characteristics of each film are generally different.5 This problem can be solved by etching the films individually, but in that case the process becomes complicated.

この発明は、上記従来の欠点を除去するためになされた
もので、高融点金属のシリサイド膜の形成およびそのパ
タニングを容易に行うことのできる半導体装置の製造方
法を提供することを目的とする。
The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can easily form a silicide film of a high melting point metal and pattern it.

以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明する。第2図(a)ないし第2図f
c)はその一実施例の工程説明図である。
Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. Figure 2(a) to Figure 2f
c) is a process explanatory diagram of one example.

まず、第2図(a)に示すように、シリコン基板21上
に熱酸化法によシ、絶縁膜としてのシリコン酸化膜22
を約100OA形成し、その上にCVD法によシボリシ
リコン膜23を約300OA形成し、通常のホトリソ工
程によシパタニングを行う。
First, as shown in FIG. 2(a), a silicon oxide film 22 as an insulating film is formed on a silicon substrate 21 by thermal oxidation.
A rough silicon film 23 having a thickness of about 300 OA is formed thereon by the CVD method, and patterning is performed by a normal photolithography process.

次に、第2図tblに示すように、ポリシリコン膜13
上に、モリブデン膜24をマグネトロンスパタツリング
によシ約300OA形成する。
Next, as shown in FIG. 2 tbl, the polysilicon film 13
A molybdenum film 24 of about 300 OA is formed thereon by magnetron sputtering.

次に、これを酸素雰囲気中にて、900℃で約30分熱
処理を行うと、ポリシリコン膜13上のモリブデン膜2
4は反応して、第2図(c)に示すように、モリブデン
シリサイド膜25となシ、シリコン酸化膜22上のモリ
ブデン膜24は酸化モリブデンとなり、蒸発する。かく
して、ポリシリコン膜23上に金属シリコン化合物電極
が形成される。なお、モリブデンシリサイド膜25上に
は酸化シリコン膜26が形成される。
Next, when this is heat-treated at 900° C. for about 30 minutes in an oxygen atmosphere, the molybdenum film 2 on the polysilicon film 13 is
4 reacts, and as shown in FIG. 2(c), the molybdenum silicide film 25 and the molybdenum film 24 on the silicon oxide film 22 become molybdenum oxide and evaporate. In this way, a metal silicon compound electrode is formed on the polysilicon film 23. Note that a silicon oxide film 26 is formed on the molybdenum silicide film 25.

以上説明したように、上記実施例では、モリブデン膜2
4がポリシリコン酸化膜23と接触している部分では、
モリブデンシリサイド膜25となるが、ポリシリコン酸
化膜23と接触しない部分はシリサイド化しない。
As explained above, in the above embodiment, the molybdenum film 2
4 is in contact with the polysilicon oxide film 23,
A molybdenum silicide film 25 is formed, but the portions not in contact with the polysilicon oxide film 23 are not silicided.

しかも、ポリシリコン酸化膜23と接触しない部分のモ
リブデン膜24は酸化され、モリブデン酸化膜は比較的
高い蒸気圧を有するρで、気化される。
In addition, the portions of the molybdenum film 24 not in contact with the polysilicon oxide film 23 are oxidized, and the molybdenum oxide film is vaporized at a relatively high vapor pressure ρ.

なお、上記実施例では、モリブデン膜24とシリサイド
を形成するために、ポリシリコン酸化膜23の薄膜を用
いだが、単結晶シリコン基板その他のシリコン膜であれ
ば同様の効果を有する。
In the above embodiment, a thin film of polysilicon oxide film 23 was used to form molybdenum film 24 and silicide, but the same effect can be obtained if a single crystal silicon substrate or other silicon film is used.

まだ、高融点金属膜として、モリブデン薄膜を用いたが
、シリコンと反応してシリサイドを形成し、かつその金
属の酸化物が比較的高い蒸気圧を有する金属であれば、
同様の効果がある。
A thin molybdenum film has been used as the high melting point metal film, but if the metal reacts with silicon to form a silicide and the metal oxide has a relatively high vapor pressure,
It has a similar effect.

以上のように、この発明の半導体装置の製造方法によれ
ば、絶縁膜上にシリコン薄膜を形成し、このシリコン薄
膜上に高融点金属を被着して酸素雰囲気中で熱処理する
ことによりシリコンと接触する部分の高融点金属をシリ
サイド化し、シリコンと接触しない部分の高融点金属を
酸化して気化させて金属シリコン化合物の電極を形成す
るようにしたので、高融点金属膜またはシリサイド膜の
エツチングを行う必要がなく、高融点金属膜のシリサイ
ド化のだめの熱処理により同時にしかもシリコン膜のパ
ターンと同一のパターンにシリサイド膜のパターンが形
成される。したがって、高融点金属膜まだはシリサイド
膜のエツチングにともなう問題点が除去され、しかも工
程が容易になると云う利点がある。
As described above, according to the method of manufacturing a semiconductor device of the present invention, a silicon thin film is formed on an insulating film, a high-melting point metal is deposited on the silicon thin film, and the silicon is heat-treated in an oxygen atmosphere. The high melting point metal in the contact area is silicided, and the high melting point metal in the area not in contact with silicon is oxidized and vaporized to form a metal-silicon compound electrode, so etching of the high melting point metal film or silicide film is not necessary. There is no need to carry out this process, and a silicide film pattern is formed at the same time and in the same pattern as the silicon film pattern by heat treatment for silicidation of the high melting point metal film. Therefore, there are advantages in that problems associated with etching high-melting point metal films and silicide films are eliminated, and the process becomes easier.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないし第1図(d)はそれぞれ従来のモリ
ブデンシリサイド膜極の形成方法の工程説明図、第2図
[a)ないし第2図fc)はそれぞれこの発明の半導体
装置の製造方法の一実施例の工程説明図である。 21・・・シリコy基板、22 、26・・・シリコン
酸化膜、23・・・ポリシリコン膜、24・・・モリブ
デン膜、25・・・モリブデンシリサイド膜。 特許出願人  沖電気工業株式会社 手続補正書 昭和57年8月31日 特許庁長官若杉和夫 殿 1、事件の表示 昭和57年 特 許 願第 42797  号2、発明
の名称 半導体装置の製造方法 3、補正をする者 事件との関係      特 許 出願人(029)沖
電気工業株式会社 4、代理人 5、補正命令の日付  昭和  年  月  日 (自
発)6、補正の対象 図面の一部 7、補正の内容 し線を別紙朱書で示すように訂正する。
FIGS. 1(a) to 1(d) are process explanatory diagrams of a conventional method for forming a molybdenum silicide film electrode, respectively, and FIGS. 2(a) to 2fc) are manufacturing steps of a semiconductor device of the present invention, respectively. FIG. 2 is a process diagram of one embodiment of the method. 21...Silicon Y substrate, 22, 26...Silicon oxide film, 23...Polysilicon film, 24...Molybdenum film, 25...Molybdenum silicide film. Patent Applicant Oki Electric Industry Co., Ltd. Procedural Amendment August 31, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1. Indication of Case 1981 Patent Application No. 42797 2. Name of Invention Method for Manufacturing Semiconductor Device 3. Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, day (self-motivated) 6, Part of drawing subject to amendment 7, Amendment Correct the content and lines as shown in red on the attached sheet.

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜上にシリコン薄膜パターンを形成してその上に高
融点金属を被着した状態で酸素雰囲気中で熱処理するこ
とによりシリコン薄膜と接触する部分の高融点金属をシ
リサイド化し、上記シリコン薄膜と接触しない部分の高
融点金属を酸化して気化させ上記シリコン薄膜上に金属
シリコン化合物電極を形成することを特徴とする半導体
装置の製造方法。
A silicon thin film pattern is formed on the insulating film, a high melting point metal is deposited on the pattern, and heat treatment is performed in an oxygen atmosphere to silicide the high melting point metal in the part that comes into contact with the silicon thin film. 1. A method of manufacturing a semiconductor device, comprising: oxidizing and vaporizing a high-melting point metal in a portion that does not contain the metal, and forming a metal-silicon compound electrode on the silicon thin film.
JP4279782A 1982-03-19 1982-03-19 Manufacture of semiconductor device Granted JPS58161344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4279782A JPS58161344A (en) 1982-03-19 1982-03-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4279782A JPS58161344A (en) 1982-03-19 1982-03-19 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58161344A true JPS58161344A (en) 1983-09-24
JPH041497B2 JPH041497B2 (en) 1992-01-13

Family

ID=12645953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4279782A Granted JPS58161344A (en) 1982-03-19 1982-03-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58161344A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315418A (en) * 1986-07-08 1988-01-22 Fujitsu Ltd Manufacture of semiconductor device
JPH0291932A (en) * 1988-09-28 1990-03-30 Fujitsu Ltd Manufacture of semiconductor device
JPH03188672A (en) * 1989-12-18 1991-08-16 Matsushita Electron Corp Charge transfer device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210672A (en) * 1975-07-15 1977-01-27 Matsushita Electric Ind Co Ltd Semi-conductor device
JPS5679433A (en) * 1979-11-30 1981-06-30 Mitsubishi Electric Corp Forming of ultra fine pattern
JPS56137675A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210672A (en) * 1975-07-15 1977-01-27 Matsushita Electric Ind Co Ltd Semi-conductor device
JPS5679433A (en) * 1979-11-30 1981-06-30 Mitsubishi Electric Corp Forming of ultra fine pattern
JPS56137675A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315418A (en) * 1986-07-08 1988-01-22 Fujitsu Ltd Manufacture of semiconductor device
JPH0291932A (en) * 1988-09-28 1990-03-30 Fujitsu Ltd Manufacture of semiconductor device
JPH03188672A (en) * 1989-12-18 1991-08-16 Matsushita Electron Corp Charge transfer device

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Publication number Publication date
JPH041497B2 (en) 1992-01-13

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