JPS5679433A - Forming of ultra fine pattern - Google Patents

Forming of ultra fine pattern

Info

Publication number
JPS5679433A
JPS5679433A JP15650579A JP15650579A JPS5679433A JP S5679433 A JPS5679433 A JP S5679433A JP 15650579 A JP15650579 A JP 15650579A JP 15650579 A JP15650579 A JP 15650579A JP S5679433 A JPS5679433 A JP S5679433A
Authority
JP
Japan
Prior art keywords
film
ultra fine
fine pattern
forming
base layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15650579A
Other languages
Japanese (ja)
Inventor
Haruhiko Abe
Natsuo Tsubouchi
Masao Nagatomo
Hiroji Harada
Junichi Mihashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15650579A priority Critical patent/JPS5679433A/en
Publication of JPS5679433A publication Critical patent/JPS5679433A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To facilitate the forming of an ultra fine pattern by a method wherein Mo film is coated on a base layer when the ultra fine pattern electrode is formed on a semiconductor, antioxide film layer is made on the film in accordance with the pattern to be left, heat treated in an oxidation atmosphere to sublimate the Mo film in the exposed area. CONSTITUTION:Mo film layer 2 is coated on a surface of the base layer 1, anitoxide film 3 such as Al film, Si3N4 film SiO2 film etc. is arranged in accordance with the desired pattern, heat treated at a temperature higher than 400 deg.C in the atmosphere of O2 of which pressure is decreased or increased, and the Mo film 2 in the exposed area is changed to the film 4 such as MoO2, MoO3 etc. Similarly, the sublimation of the film 4 is used to sublimate the same to keep the Mo film 2 of ultra fine pattern only below the film 3. With this arrangement, regardless of the material quality of the base layer, a forming of the ultra fine pattern can be facilitated.
JP15650579A 1979-11-30 1979-11-30 Forming of ultra fine pattern Pending JPS5679433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15650579A JPS5679433A (en) 1979-11-30 1979-11-30 Forming of ultra fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15650579A JPS5679433A (en) 1979-11-30 1979-11-30 Forming of ultra fine pattern

Publications (1)

Publication Number Publication Date
JPS5679433A true JPS5679433A (en) 1981-06-30

Family

ID=15629222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15650579A Pending JPS5679433A (en) 1979-11-30 1979-11-30 Forming of ultra fine pattern

Country Status (1)

Country Link
JP (1) JPS5679433A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161344A (en) * 1982-03-19 1983-09-24 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPS63127641U (en) * 1986-08-12 1988-08-22
CN102583544A (en) * 2012-02-08 2012-07-18 中国矿业大学 Method for preparing molybdenum trioxide by utilizing waste silicon molybdenum rod

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161344A (en) * 1982-03-19 1983-09-24 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH041497B2 (en) * 1982-03-19 1992-01-13 Oki Electric Ind Co Ltd
JPS63127641U (en) * 1986-08-12 1988-08-22
CN102583544A (en) * 2012-02-08 2012-07-18 中国矿业大学 Method for preparing molybdenum trioxide by utilizing waste silicon molybdenum rod

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