JPS58159350A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58159350A
JPS58159350A JP4170082A JP4170082A JPS58159350A JP S58159350 A JPS58159350 A JP S58159350A JP 4170082 A JP4170082 A JP 4170082A JP 4170082 A JP4170082 A JP 4170082A JP S58159350 A JPS58159350 A JP S58159350A
Authority
JP
Japan
Prior art keywords
film
insulating film
etching
semiconductor device
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4170082A
Other languages
Japanese (ja)
Inventor
Takayuki Matsui
孝行 松井
Jun Kanamori
金森 順
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4170082A priority Critical patent/JPS58159350A/en
Publication of JPS58159350A publication Critical patent/JPS58159350A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the highly accurate mask pattern for the titled semiconductor device by a method wherein, after a CVD insulating film consisting of a PSG film had been formed, the surface of said insulating film is smoothed, and subsequently a CVD insulating film is formed again, thereby enabling to accomplish a high degree of smoothness of the surface of the CVD insulating film. CONSTITUTION:A photoresist film 7is formed slightly thin in thickness at the projected part 8 of the PSG film and slightly thick in thickness at the other part. Then, a dry etching is performed to the photoresist film 7 until the projected part 8 is exposed. A selective etching is performed on the above covexed part 8 using the photoresist film 7, whereon an etching was performed, as a mask and the smooth surface of the CVD insulating film 6 consisting of a PSG film is formed. Regarding the etching to be performed on the roughened part of said PSG film, when an over-etching is performed to some extent, a part 10 of the convexed section 8 only is somewhat overetched, and when the photoresist film 7 is removed, the smooth surface of a CVD insulating film 11, consisting of the first aluminum 6, can be formed on the region where the film is to be thickly formed.

Description

【発明の詳細な説明】 本発明は半導体装置の多層配線形成を改良して成る半導
体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device by improving the formation of multilayer wiring in the semiconductor device.

従来、半導体装置の多層配線形成は、第1金属配線を形
成した後、絶縁膜をCVD法(へ相継法)等によシ被着
し、スルーホールを形成し、しかる後、第2金属配線を
形成するものであるが、この方法には第1金属配線段差
がs、ooo〜12,0OOAと大きく、XCVD法等
の絶縁膜の被着時にオーバーハング構造になるなどの欠
点があシ、そのtま第2金属配線を行なった場合に、そ
の段差部においてステップカバレンジ不良によシ断線と
いう不良事態が発生するという問題があつ九。これら問
題の解決法として平滑な多層配線f5氏が考えられてい
る。
Conventionally, in the formation of multilayer wiring for semiconductor devices, after forming a first metal wiring, an insulating film is deposited by a CVD method (fabric succession method) or the like to form a through hole, and then a second metal wiring is formed. However, this method has drawbacks such as the first metal wiring step being as large as s,ooo to 12,0OOA, and resulting in an overhang structure when depositing an insulating film using the XCVD method. However, if the second metal wiring is performed until that time, there is a problem in that a faulty situation such as wire breakage occurs due to poor step coverage at the stepped portion. As a solution to these problems, smooth multilayer wiring f5 is being considered.

以下に、半導体装置の多層配線形成の二従来例を第1図
、第2図と共に説明する。
Two conventional examples of forming multilayer wiring in a semiconductor device will be explained below with reference to FIGS. 1 and 2.

第1図は前記多層配線形成の従来例を示し、lは半導体
基板、2はAI配線、3はポリイミド系樹脂の絶縁膜で
ある。この方法はまず半導体基板1上にA!配線2を装
着形成し、凸状部線薄く、他の部分は厚くなるように塗
布させる前記ポリイミド系樹脂3の塗布特性を利用して
、前記ポリイミド系樹脂3の平滑な表面を形成せしめる
もので、処理工程は少ないが、それだけに表面平滑化の
精度は萬〈ない。
FIG. 1 shows a conventional example of multilayer wiring formation, in which 1 is a semiconductor substrate, 2 is an AI wiring, and 3 is an insulating film made of polyimide resin. In this method, A! A smooth surface of the polyimide resin 3 is formed by using the coating characteristics of the polyimide resin 3, which is applied so that the wiring 2 is attached and formed, and the convex part is thin and the other parts are thick. Although the number of processing steps is small, the accuracy of surface smoothing is not guaranteed.

第2図は前記多層配線形成工程の他の従来例を示し、1
は半導体基板、2はA4配線、4はPSG膜をCVD法
で被着せしめるCVD@縁りはホトレジストあるいはポ
リイミド系樹脂で形成され九有機物被膜である。この方
法は、まず第2図(a)の如く、半導体基板1上にAj
配線2を装着形成し、その上にCVD絶縁膜4を厚目に
育成した後、有機物被膜5を塗布し、次に前記有機物被
膜5と前記(至)絶縁膜4をほぼ同一のエツチング速度
でプラズマエツチングし、さらに第2図(b)の如く、
前記CVD絶縁膜4を若干エツチングしてその表面を平
滑化せしめるもので、上述の最初の従来例に比し、表面
の平滑化の精度は上る。ただし、上述の有機物被膜5及
びCVD@縁膜4の両者に対してほぼ同−c7) エフ
 f y / 速fで行われるプラズマエツチングの方
法は、これらの膜質のバラツキにょシエッチング速度に
変化が生じ、実際のところ、前記の同一エツチング速度
を維持することは技術的に困難である。すなわち、この
場合、前記絶縁膜4及び有機物被膜5に対して圧力、ガ
ス、流菫、前把手そゎよ対、しア、ッ、7ケ、度8変−
タ4bを得ないために、エツチング速度の制御は技術的
に非常に難しいH亀である。
FIG. 2 shows another conventional example of the multilayer wiring forming process, 1
2 is a semiconductor substrate, 2 is an A4 wiring, and 4 is a PSG film coated by the CVD method.The edges are made of photoresist or polyimide resin and are an organic coating. In this method, first, as shown in FIG. 2(a), Aj is placed on a semiconductor substrate 1.
After forming the wiring 2 and growing a thick CVD insulating film 4 thereon, an organic film 5 is applied, and then the organic film 5 and the insulating film 4 are etched at approximately the same rate. After plasma etching, as shown in Fig. 2(b),
The CVD insulating film 4 is slightly etched to smooth its surface, and the accuracy of surface smoothing is improved compared to the first conventional example mentioned above. However, the plasma etching method, which is performed at approximately the same speed f for both the organic film 5 and the CVD film 4 described above, does not change the etching rate due to variations in the quality of these films. In fact, it is technically difficult to maintain the same etching rate. That is, in this case, the insulating film 4 and the organic film 5 are subjected to pressure, gas, violet, front handle, 7 pieces, 8 degrees of change.
It is technically very difficult to control the etching speed so as not to obtain the etching pattern 4b.

さらに、上述の二従来例において、ポリイミド系樹脂を
絶縁膜として用いた場合には、樹脂の中に含まれる不純
物、例えば塩素などにより素子特性が劣化したシ、ある
いは金属配線が腐蝕するという間趙も発生した。
Furthermore, in the two conventional examples mentioned above, when polyimide resin is used as the insulating film, impurities contained in the resin, such as chlorine, may deteriorate the device characteristics or corrode the metal wiring. also occurred.

本発明は叙上の点に着目して成されたもので、半導体装
置の多層配線形成において、不純物汚染や難しいエツチ
ング技術を必要とせず、しかも表面を高い精度で平滑化
できる半導体装置の製造方法を提供することを目的とす
るものである。
The present invention has been made by focusing on the above-mentioned points, and is a method for manufacturing a semiconductor device that does not require impurity contamination or difficult etching techniques in the formation of multilayer wiring in a semiconductor device, and can smooth the surface with high precision. The purpose is to provide the following.

以下に、本発明の一実施例を第3図と共に説明する。An embodiment of the present invention will be described below with reference to FIG.

第3図は、本発明の一実施例で、多層配線形成の工程を
示し、lは半導体基板、2はAI配線、6゜11はPS
G膜で、前記CVD法で被着せしめてCVD絶縁膜とな
る。7はホトレジスト膜、8はPSG膜凸膜部状部はP
SG膜下部表面、10はPSG膜オーバーエツチング部
である。
FIG. 3 is an embodiment of the present invention, showing the process of forming multilayer wiring, where l is a semiconductor substrate, 2 is an AI wiring, and 6°11 is a PS
The G film is deposited by the CVD method described above to become a CVD insulating film. 7 is a photoresist film, 8 is a PSG film, and the convex film portion is P.
On the lower surface of the SG film, reference numeral 10 indicates an over-etched portion of the PSG film.

本発明の方法は、まず第3図(a)に示すように、半導
体基板1′上にAI配線2を装着形成し、前記C■法に
よJ)PSG膜を前記An配線2とほぼ同じ膜厚になる
ように被着せしめてCVD絶縁膜6を形成し、その上に
ホトレジスト膜7を形成する。このホトレジスト膜7は
、通常の塗布特性によりPSG膜凸状部8では薄目に、
他の部分では厚目に形成される。次に、第3図(b)に
示すように前記凸状部8が露出するまでホトレジスト膜
7をドライエツチングする。そして、このエツチングさ
れたホトレジスト膜7をマスクとして前記凸状部8を選
択的にエツチングし、第3図(c)に示すようにPSG
膜より成るCVD絶縁膜6の平滑な表面を形成する。こ
のPEG膜凸膜部状部8ツチングは、多少オーバーエツ
チングを行なっても、ht配線2の部分はエツチングさ
れないため、前記凸状部8であった所の一部分10のみ
が余計にオーバーエツチングされるのみであり、第3図
(d)に示すように、前記ホトレジス)M17を除去し
、さらにPSG膜を再度被着させることによ如、第3図
(e)に示す如きP S GMよシ成るCVD絶縁膜1
1の平滑な表面を形成する仁とができる。
In the method of the present invention, first, as shown in FIG. 3(a), an AI wiring 2 is mounted and formed on a semiconductor substrate 1', and then a PSG film is deposited using the C method described above, which is almost the same as the An wiring 2. A CVD insulating film 6 is formed by depositing the same film thickness, and a photoresist film 7 is formed thereon. This photoresist film 7 is thinner on the PSG film convex portion 8 due to normal coating characteristics.
It is thicker in other parts. Next, as shown in FIG. 3(b), the photoresist film 7 is dry-etched until the convex portion 8 is exposed. Then, using this etched photoresist film 7 as a mask, the convex portion 8 is selectively etched to form a PSG film as shown in FIG. 3(c).
A smooth surface of the CVD insulating film 6 made of a film is formed. In this PEG film convex film portion 8 etching, even if some overetching is performed, the ht wiring 2 portion is not etched, so only a portion 10 where the convex portion 8 was previously etched is excessively overetched. As shown in FIG. 3(d), by removing the photoresist (M17) and re-depositing the PSG film, a PSG film as shown in FIG. 3(e) can be obtained. CVD insulating film 1 consisting of
A layer forming a smooth surface is formed.

なお、上述の実施例においては、有機物被膜としてホト
レジスト膜を使用した場合を述べたが、これはポリイミ
ド系樹脂等の他の有機物質を用いても何ら問題はない。
In the above embodiments, a photoresist film was used as the organic film, but there is no problem in using other organic materials such as polyimide resin.

以上説明したように、本発明の実施例はホトレジスト膜
7のパターンをパターン合わせ、露光等の工程を省いて
エツチングのみで形成することができる。しかも、この
方法は前記PSG膜凸膜部状部みを選択的にエツチング
することを特徴としたもので、第2図の上述の従来例の
ように、前記ポリイミド系樹脂膜と前記PSG膜とをほ
ぼ同一のエツチング速度でエツチングさせなければなら
ないために直面した上述の技術的困難を全く避けること
ができる。またPSG膜より成る前記CVD絶縁膜60
オーバー、エツチングが可能であるため、エツチング条
件がかなり緩和されるという利点がある。
As explained above, in the embodiment of the present invention, the pattern of the photoresist film 7 can be pattern-aligned, and steps such as exposure can be omitted and the pattern can be formed only by etching. Moreover, this method is characterized by selectively etching only the convex film portions of the PSG film, and as in the above-mentioned conventional example shown in FIG. The above-mentioned technical difficulties encountered due to having to etch at approximately the same etching speed can be completely avoided. Furthermore, the CVD insulating film 60 is made of a PSG film.
Since over-etching is possible, there is an advantage that the etching conditions are considerably relaxed.

さらにまた、使用する有機物質は最終的には除去してし
まうものであるから、111図の上述の従来例のように
有機物質中の不純物のために半導体特性に影替を受ける
心配がないという利点もある。
Furthermore, since the organic material used is ultimately removed, there is no need to worry about the semiconductor properties being affected by impurities in the organic material, as in the conventional example shown in Figure 111. There are also advantages.

以上説明し友とおシ、本発明は、半導体装置の凸状部の
薄い該有機物被膜のみをプラズマエツチングして前記C
VD絶縁膜表面の平滑化を行い、しかる後再[CVD絶
縁膜を育成することにより、技術的に困難なエツチング
を必要とせずにCVD絶縁膜表面の高度な平滑化を実現
し、その結果、従来の不純物汚染や金属配線の層間段差
の間亀を解決できるという効果を書するものである。し
かも、この高度な表面平滑化技暫によって、本発明は半
導体装置の多層配線の層間絶縁膜形成の方法として広い
利用価値を得ることができ、さらに本発明の方法によっ
て平滑な絶縁膜の表面上に塗布したホトレジスト膜が凹
凸のない均一な膜厚として得られるため、本発明は高精
度なマスクパターンを得るための技術的手段としても広
く応用できるという順著な技術的効果を有するものであ
る。
Having explained the above, to my friend, the present invention involves plasma etching only the thin organic film on the convex portion of a semiconductor device.
By smoothing the surface of the VD insulating film and then growing the CVD insulating film again, it is possible to achieve a high degree of smoothing of the surface of the CVD insulating film without the need for technically difficult etching. This paper describes the effect of solving the problems of conventional impurity contamination and interlayer differences in metal wiring. Moreover, by using this advanced surface smoothing technique, the present invention can be widely used as a method for forming an interlayer insulating film in multilayer wiring of semiconductor devices. Since the photoresist film coated on the photoresist film can be obtained with a uniform film thickness without unevenness, the present invention has a remarkable technical effect that it can be widely applied as a technical means for obtaining a highly accurate mask pattern. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示す半導体装置の多層配線断面図、第
2図は従来例を示す半導体装置の多層配線形成の工程図
、第3図は本発明の実施例を示す半導体装置の多層配線
形成の工程図である。 1・・・半導体基板、2・・・A)配線、6,11・・
・PSG膜より成るCVD絶縁膜、7・・・ホトレジス
ト膜、8・・・PSG膜凸膜部状 部許出願人 沖電気工業株式会社 第1図 第2図 第3図 手続補正書 昭和57年6月30日 特許庁長官 fr参和夫殿 1、事件の表示 昭和s1年 畳 許 願第0417002、俺@04称 亭導体装置の調造、IF法 3、補正をする者 事件との関係    轡 許 出願人 (0!*)神電気工*微式会社 4、代理人 5、補正命令の日付  昭和  年  月  日(麿−
)6、補正の対象 @lll書Or 弗moWIA傘説@ J O欄及び「
1SO簡単なI!@JO橢。 (i)  明細書第2頁18行ないし20行の「処理工
程は少ないが、それだけに表面平滑化の1′#1度は茜
(ない。」t−「絶縁膜としてポリイミド系樹脂を用い
るために、樹脂の中に含まれる不純物、例えば塩素など
により素子特性が劣化したり、あるいは金属配線が腐蝕
するという問題が発生した。」と訂正する。 (2)  −書第3頁12行ないし13行の「表面の平
滑化の精度は上る。」を「ポリイミド系樹脂全最終的に
取り除く几め、樹脂中に含まれる不純物による劣化は生
じない。」と訂正する。 (3)四書第4頁6行ないし10行の「さらに、上述の
二従来例において、ポリイミド系樹脂を絶縁膜として用
いた場合には、樹脂の中に含まれる不純物、ガえは塩素
などにより素子特性が劣化し九り、あるいは金属配線が
腐蝕するという問題も発生し友。Jを削除する。 (4)同iFS画10行の「池の部分Jt−r他の部分
9」と訂正する。 (5)同書8頁11行のrPSG編凸状部。」tr P
 8 G@凸状1[、e−P 8 Gl[下1!表面、
10、・・P8G膜オーバーエツチング部」と訂正する
、。 以上
FIG. 1 is a cross-sectional view of multilayer wiring of a semiconductor device showing a conventional example, FIG. 2 is a process diagram of forming multilayer wiring of a semiconductor device showing a conventional example, and FIG. 3 is a multilayer wiring of a semiconductor device showing an embodiment of the present invention. It is a process chart of formation. 1... Semiconductor substrate, 2... A) Wiring, 6, 11...
・CVD insulating film made of PSG film, 7... Photoresist film, 8... PSG film convex film portion Applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Figure 3 Procedure amendment 1982 June 30th, Commissioner of the Patent Office, Mr. Kazuo San 1, Indication of the case, Showa S1, Tatami Permit Application No. 0417002, Preparation of conductor device, IF Act 3, Person making amendment, Relationship with the case Applicant (0!*) Kami Electric Co., Ltd. 4, agent 5, date of amendment order Showa year, month, day (Maro-
) 6. Subject of correction @llll book or ⑗moWIA umbrella theory @ J O column and “
1SO easy I! @JO 橢. (i) On page 2 of the specification, lines 18 to 20, ``The number of processing steps is small, but that is why the surface smoothing is done once.'' t - ``In order to use polyimide resin as an insulating film.'' , there have been problems such as impurities contained in the resin, such as chlorine, deteriorating the device characteristics or corroding the metal wiring.'' (2) - Book, page 3, lines 12 and 13. ``The accuracy of surface smoothing increases.'' is corrected to ``If the polyimide resin is completely removed, no deterioration will occur due to impurities contained in the resin.'' (3) Book 4, page 4 Lines 6 to 10: ``Furthermore, in the two conventional examples mentioned above, when polyimide resin is used as the insulating film, impurities and gags contained in the resin deteriorate the device characteristics due to chlorine, etc. , or there may be a problem of corrosion of the metal wiring, so delete J. (4) Correct line 10 of the same iFS image to "Pond part Jt-r other part 9". (5) Same book, page 8 11 rows of rPSG convex parts.”tr P
8 G@Convex 1[, e-P 8 Gl[Lower 1! surface,
10,... P8G film over-etched part" is corrected. that's all

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の多層配線形成工程で金属配線の形成と、こ
の金属配線に絶縁膜の被着とを行わしめる半導体装置の
製造方法において、前記絶縁膜の被着後、該絶縁膜の表
面上に凸状部社薄く、他の部分は厚く形成せしめる有機
物被膜の塗布と、前記絶縁膜の凸状部が露出するまで行
わしめる前記有機物被膜の均一エツチングと、前記有機
物被膜をマスクとして行わしめる前記絶縁膜の選択的エ
ツチングと、前記絶縁膜の再被着とを順次行わしめるこ
とを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device in which a metal wiring is formed and an insulating film is deposited on the metal wiring in a multilayer wiring forming process of the semiconductor device, after the insulating film is deposited, a protrusion is formed on the surface of the insulating film. Applying an organic film thinly and thickly on other parts, uniformly etching the organic film until the convex portions of the insulating film are exposed, and etching the insulating film using the organic film as a mask. 1. A method of manufacturing a semiconductor device, comprising sequentially performing selective etching of the insulating film and re-deposition of the insulating film.
JP4170082A 1982-03-18 1982-03-18 Manufacture of semiconductor device Pending JPS58159350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4170082A JPS58159350A (en) 1982-03-18 1982-03-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4170082A JPS58159350A (en) 1982-03-18 1982-03-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58159350A true JPS58159350A (en) 1983-09-21

Family

ID=12615692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4170082A Pending JPS58159350A (en) 1982-03-18 1982-03-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58159350A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04188733A (en) * 1990-11-21 1992-07-07 Sharp Corp Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56148845A (en) * 1980-04-22 1981-11-18 Toshiba Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56148845A (en) * 1980-04-22 1981-11-18 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04188733A (en) * 1990-11-21 1992-07-07 Sharp Corp Manufacture of semiconductor device

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