JPS5893354A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the coverage of step of multipolar wiring structure largely by sputtering and etching a layer insulating film formed through a CVD method by inert gas ions. CONSTITUTION:When Ar gas is RF-sputtered onto the insulating film 4 shaped onto the first layer electrode wiring 31 in AlSi through the CVD method, Ar<+> ions are projected to a semiconductor substrate 1 approximately vertically. A sputtering phenomenon by Ar<+> ions, etc. largely depends upon an incident angle, and the etching rate is increased in an approximately quintuple extent when the ions are projected at approximately 45 deg. as compared to when they are projected vertically. Accordingly, the etching of a stepped section advances abnormally rapidly as compared to flat sections in the sputtering and etching of the insulating film 4, and the excellent sectional form of the coverage of step is obtained in shape after etching.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming an interlayer insulating film for multilayer metal wiring.

FIGS. 1 and 2 are cross-sectional views showing one step in the manufacturing method of this type of conventional device.

Conventional interlayer insulating films are formed using, for example, carbon dioxide using SiH4 and 02 as material gases on electrode wiring formed of AIS {alloy.
Si02 was grown using the VD method at a growth temperature of about 480°C. In reality, Si02 with a thickness of about 1 μm has drawbacks such as being prone to cracking, and non-doped S
Instead of i02, phosphorus glass containing phosphorus is grown. However, as shown in FIG. 1, the insulating film (4) made of Si02 or phosphor glass does not have good shape so-called step coverage of the edge portion of the electrode wiring (b) formed of AISi alloy. Insulating film 《4
As shown in FIG. 2, the second layer electrode wiring (self) formed at t had a fatal defect in that it was easily disconnected.

In addition, in FIGS. 1 and 2, <<1>> represents a semiconductor substrate,
(101) is a region formed on the substrate (1), and the first electrode wiring 01) is electrically connected to the region (101). This improves the step coverage at the edge of the AlSi electrode wiring. Therefore, various improvements have been made to the CVD method, and low pressure CVD and plasma CVD are now being used instead of normal pressure CVD. °C markedly improved. For this reason, in the case of two-layer wiring, it has become possible to form an insulating film with a fairly high yield by using the plasma CVD method. However, due to various level differences on the semiconductor substrate, it is necessary to set many restrictions on the two-layer wiring pattern. Further, in the case of three-layer wiring, even larger steps occur, so even if plasma CVD is used, step coverage is insufficient.

The present invention has been made in order to improve the step coverage of the interlayer insulating film formed by the conventional CVD method as described above. It is an object of the present invention to provide a semiconductor device having a multilayer electrode wiring structure with significantly improved step coverage.

An embodiment of the method of the present invention will be described below with reference to FIG.

In fM8 diagram (4) °r, n) is the semiconductor substrate, (2)
01 is the 111th electrode wiring of AlSi, which is a region formed on the semiconductor substrate (not shown)
It is connected to the. (4) is an interlayer insulating film such as phosphor glass or silicon nitride. +6) is a low energy Au+ used for sputter etching of the glabella insulating film (4).
Ions are represented by arrows.

As shown in Figure 8 (to), when RF sputtering is performed using Ar gas on the insulation WI4 (4) formed by CVD on the AlSi @1 layer electrode wiring (b), the semiconductor substrate +1)- Ar"<on is incident almost vertically. Sputtering development by Ar+ ions, etc. strongly depends on the angle of incidence, as shown in Figure 4. When the incidence is about 46 degrees in the dark, the incidence is greater than when the incidence is perpendicular. , the etching rate increases by about 6 times.For this reason, the sputter etching of the insulating film (4) is
Etching of the step portion progresses abnormally faster than that of the flat portion, and after etching, a cross-sectional shape with very good step coverage as shown in FIG. 8 can be obtained.

FIG. 5 shows 118EM cross-sectional photographs before and after sputter etching. FIG. 6(2) shows a cross-sectional photograph before sputter etching, and FIG. 6 (F)) shows a cross-sectional photograph after sputter etching. The improvement in step coverage is noticeable as seen from the 88M photo.

FIG. 6 shows a schematic diagram of the configuration of the RS spats and equipment used for spacks etching. In FIG. 6, 'C1 (6) is the lower ionization (susceptor), % (7) is the upper electrode, (8) is the semiconductor substrate, (9) is the plasma, and (d) is the RF power source.

FIG. 7 is a cross-sectional view showing the process of two-layer wiring according to an embodiment of the present invention in order of process. As shown in the seventh drawing, on the semiconductor substrate (1) on which the first layer electrode wiring (2) has been completed,
Form an insulating film (4) between the eyebrows using the CVD method, and form a through hole Q11 using photolithography (0°).Next, introduce the semiconductor substrate (1) into the sputtering equipment and perform RF sputtering in Ar gas. The step coverage of the stepped portion is improved (2).AlSi sputtering is also incorporated in the sputtering equipment, so after the sputter etch is completed, a second layer of AlSi is deposited in the same equipment. , forming a two-layer wiring (2) (see E in the same figure) - In this method, the surface of the first layer Al5 (at the through hole (11)) is also etched with a spat 9, but the amount is usually about 0.7 μm. This amount is not a problem.Furthermore, the step at the opening of the through-hole portion is also sputter-etched to form a 'C taper shape, and the cutting ratio at the through-hole portion is greatly improved.

In addition, in the embodiment described in section t, the description was given to a multilayer wiring structure, but the explanation is also given to a structure that requires flattening of the film, such as a tertiary element element.
The present invention also has the same effects as the above embodiments.

As described above, according to the present invention, by sputter-etching the interlayer insulating film, the step coverage at the stepped portion is significantly improved, which has the effect of improving the disconnection rate in multilayer wiring. In addition, by performing sputter etching in the same equipment immediately before sputtering such as AIS i, the above effects can be obtained without complicating the process and without requiring special equipment. The manufacturing advantage is very large.

[Brief explanation of the drawing]

FIG. 1 is a cross section showing the step coverage of the glabellar insulating film formed by the conventional CVD method. Figure 2 is a cross-sectional view showing a broken part of the two-layer wiring at a step in the same aircraft. @Figure 8 is a cross-sectional view showing recasting of step coverage of a stepped portion by sputter etching according to the method of the present invention. FIG. 4 is a diagram showing the dependence of etching rate on incident angle. Fifth
The figure shows cross-sectional SEM photographs before and after sputter etching. 6th
The figure is a schematic diagram of the configuration of a sputter etching apparatus. FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a two-layer wiring structure according to an embodiment of the present invention. In the figure, 1) is the semiconductor substrate, (101) is the region, and (2)
is Si02, @(2) is AlSi electrode wiring, (4) is an insulating film, +6) is a - ion, (6) is a lower electrode, (7
] is a ha electrode, (8) is a semiconductor substrate, (9) is a plasma, (11) is an RF power source, and a is a suru. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Patent Attorney Makoto Shimano - '1 Fig. 1 Fig. 2 Fig. 3 Fig. 4 Angle of incidence Fig. 5 Fig. 6 Fig. 7 Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Indication of case Patent application Showa 1 $6-114-08 No. 3, person making the amendment 6, detailed description of the invention column 6 of the specification to be amended, and the description of the contents of the amendment are amended as follows. Page line correction Previous correction
Positive 4 12 Au+Ar+ 61 11 RS sputter RF sputter 6i80.7μm0.1μm □ 6111 Breakage rate □ ) Procedural amendment (traveling) 57 stanza N June 27, 1939 1, Indication of incident Patent application 56-1947011
issue. 2. Title of the invention Semiconductor device manufacturing method 3. Relationship with the case of the person making the amendment Patent applicant 6. Subject of the amendment (1) Brief description of drawings in the specification (2) Drawing 7. Amendment Contents+11 In the 7th page, line 12 to 1st digit of the specification, the phrase ``Figure 6 shows...'' was replaced with ``Figure 5 (3) shows the semiconductor crystal structure before sputter etching. SEM showing the cross section of
The photograph and FIG. 5(B) are SEM photographs showing a cross section of the semiconductor crystal structure after sputter etching.'' (Figure 5 of the 21 drawings is amended as shown in the attached sheet.) 1 Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office 1. Indication of the case Relationship to the patent application No. 1984 TOI case Patent applicant address Tokyo 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent address 2-2-3-6 Marunouchi 2-chome, Chiyoda-ku, Tokyo Subject of amendment (1) Detailed Description of the Invention in the Specification Column (2) Drawing 6 Contents of Amendment (1) On page 4, line 12 of the middle cylinder of the specification, l'-AU"J is corrected to "Ar"J. (2) In the same page, page 6!l! Line 7, the phrase "Cross-sectional photograph showing the state before sputter etching" is corrected to "51M photograph showing the cross section of the semiconductor crystal structure before sputter etching." ( 3) In the 8th line of page 6, the phrase "A cross-sectional photograph after sputter etching is shown." is corrected to "A 51M photograph showing a cross section of the semiconductor crystal structure after sputter etching is shown." ( 4) Same, on page 6, line 11, replace RSJ with RF
Correct it with J. (5) Same, page 6, line 8, 1'C, "0.'lpm J" is corrected to "o, 1 μm". (6) In the same article, page 6, line 11, the phrase “new graduate rate” was replaced with “
The disconnection rate is corrected. (7) Among the drawings, the fifth drawing will be corrected as shown in the attached sheet. Above 1.1 ,,″□゛

Claims (1)

[Claims] 1. After forming an insulating film such as a silicon oxide film, phosphorous glass, or silicon nitride film on the electrode wiring by CVD or plasma CVD, the insulating film is sputtered to form a predetermined film. A method for manufacturing a semiconductor device characterized by etching the etching thickness. 2. On the electrode wiring by CVD method or plasma CVD method,
After forming an insulating film such as a silicon oxide film, a phosphorus glass film, or a silicon nitride film, and opening a through hole in the insulating film, etching the film to a predetermined thickness using a sputtering method, and then forming wirings such as A1. A method for manufacturing a patented device characterized by depositing a material by sputtering or the like. 8. The method of manufacturing a semiconductor device according to claim 2, wherein the sputter etching of the insulating film and the sputtering of the wiring material such as A1 are performed successively in the same apparatus.