JPS584948A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS584948A
JPS584948A JP10288081A JP10288081A JPS584948A JP S584948 A JPS584948 A JP S584948A JP 10288081 A JP10288081 A JP 10288081A JP 10288081 A JP10288081 A JP 10288081A JP S584948 A JPS584948 A JP S584948A
Authority
JP
Japan
Prior art keywords
wiring
layer
amorphous
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10288081A
Other languages
Japanese (ja)
Inventor
Kanetake Takasaki
高崎 金剛
Kenji Koyama
小山 堅二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10288081A priority Critical patent/JPS584948A/en
Publication of JPS584948A publication Critical patent/JPS584948A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve corrosion resistance by a method wherein an Al wiring is covered by an amorphous Si layer and then by a PSG layer. CONSTITUTION:An Al film 2' on an Si substrate 1 is deposited wth an amorphous Si layer 3' by the CVD method. A coating of PSG 4 is laid down after patterning. Or, an amorphous Si layer 3' and then a PSG layer 4 may be laid down after the formation of an Al wiring 2. This setup greatly improves the Al wiring corrosion resistance.

Description

【発明の詳細な説明】 本発明は半導体装置、特にアルミニウム(ムt)配線の
保−膜としてアモルファスシリコン膜が形成された半導
体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which an amorphous silicon film is formed as a protective film for aluminum (mut) wiring.

半導体装置の高集積密度化が進む中でAtの配線幅もそ
れに応じて縮少し、現在でIl′i3(μm)以下の微
細線幅のものが実用化されるに至りてお9、同様に配線
高さく厚さ)も6000 (X )〜1 (am)を極
薄化の傾向をたどっている。かかるAt配線の上には保
護膜としてりん・・シリケート・ガラス(PSG )層
を堆積することが一般に行われ、ps。
As the integration density of semiconductor devices continues to increase, the width of At interconnects has also decreased accordingly, and today, lines with fine line widths of Il'i3 (μm) or less have been put into practical use9. The wiring height and thickness also follow the trend of becoming extremely thin, ranging from 6000 (X) to 1 (am). A phosphorus silicate glass (PSG) layer is generally deposited as a protective film on such At wiring, and ps.

層はムを配線の絶縁膜となるだけでなく、At配線を外
部雰囲気から保饅しかつそれを補助する機能を果たして
いる。しかし、現KfI気の多い雰囲気の中でFiP8
Gと水分が反応してリン酸が生成し、仁れがAt配線を
腐食させるという問題が発生し、特に最近の極薄配線に
おいては腐食によりムtが断線するなど致命的事故の原
因となり、その対策が望まれている。更に1ムL配線の
シンタリングの関にALの表面に突起が発生し、この突
起がP2O層に入って上記の問題を悪化させる。
The layer not only serves as an insulating film for the Atmium wiring, but also functions to protect and assist the Atm wiring from the external atmosphere. However, in the current KfI atmosphere, FiP8
When G and moisture react, phosphoric acid is produced, and the problem arises that the nicks corrode the At wiring.Especially in the case of the latest ultra-thin wiring, corrosion can cause fatal accidents such as wire breakage. Countermeasures are desired. Furthermore, protrusions are generated on the surface of the AL due to the sintering of the 1 µL wiring, and these protrusions enter the P2O layer, aggravating the above-mentioned problem.

本発明は上記腐食額策として、At配線の上面または上
面と両側面上にアモルファスシリコン(アモルファスS
i)膜を形成し、その上K PSG層を形成するという
At配線の保護膜の二重構造により耐食性を向上させる
ことを目的とし、そのためのアモルファス81膜が形成
された半導体装置を提供する。
As a countermeasure against corrosion, the present invention provides amorphous silicon (amorphous S) on the top surface or the top surface and both side surfaces of the At wiring.
The purpose of the present invention is to provide a semiconductor device in which an amorphous 81 film is formed for the purpose of improving corrosion resistance by a double structure of a protective film for At wiring, in which a film is formed and a K PSG layer is formed thereon.

以下、本発明の実施例を図面−にしたがって説明す息。Hereinafter, embodiments of the present invention will be described with reference to the drawings.

j111図は、本発明に従う半導体装置を製造するため
のAt配線と保−膜を形成する工程にシけるAA配線の
1膜部を示し、図において、it!その上にムを配線が
形成される下地例えばウェハであり、先ずウェハ1の全
面上にアルミニウム膜2′を蒸着によって堆積する( 
(a) )、さらにその上にアモルファス81属3′を
200〜1000(X)の厚さに堆積する[ (b) 
)、ここで、アモルファス81 @ 3’の堆積は一般
KFifラズマ化学気相成長(CVD )法によって行
うが、ムtの軟化する温度(約450℃)以下で行うこ
とが重要である。それ以外にも、例えばスノ譬ツタリン
グ法、エレクトロン・ビーム蒸着法またはイオン・ビー
ム・デ4ジッシ、ン法などいずれの方法によってもよい
、続いて、通常の技術で配線ノ量ターンに応じアモルフ
ァス8I j[3’とAj膜2′のΔターニングを行い
、その上にアモルファスs量属3がのったAt配線2を
形成し〔(−)〕、最後にウニ八表面全面上K P8G
層4を成長させる((d))。
Figure j111 shows one film part of the AA wiring in the step of forming an At wiring and a protective film for manufacturing a semiconductor device according to the present invention. The substrate on which wiring is formed is, for example, a wafer. First, an aluminum film 2' is deposited by vapor deposition on the entire surface of the wafer 1.
(a)), and further deposit amorphous 81 genus 3' on top of it to a thickness of 200 to 1000 (X) [(b)
), here, the deposition of amorphous 81@3' is performed by the general KFif plasma chemical vapor deposition (CVD) method, and it is important to perform the deposition at a temperature below the softening temperature of Mut (approximately 450° C.). In addition, any other method may be used, such as the solar casing method, the electron beam evaporation method, or the ion beam deposition method.Subsequently, the amorphous 8I film is formed using a conventional technique depending on the amount of wiring. ∆ turning of J [3' and Aj film 2' is performed, At wiring 2 with amorphous s-metal 3 is formed thereon [(-)], and finally K P8G is formed on the entire surface of Urchin 8.
Grow layer 4 ((d)).

かかる工程により、ht配線2の上面のみにアモルファ
スsi膜3とPBG層402重の保護膜が形成され、問
題となる薄肉方向の腐食は十分に防止し得るものである
が、さらにAt配線の側面部も含めて完全な耐食構造と
したい場合KF1tli 2図に示す本発明の他の実施
例を利用しうる。
Through this process, a protective film layered with the amorphous Si film 3 and the PBG layer 402 is formed only on the upper surface of the HT wiring 2, and corrosion in the thinner direction, which is a problem, can be sufficiently prevented. If a complete corrosion-resistant structure is desired including the parts, another embodiment of the present invention shown in Fig. 2 can be used.

すなわち、j112図に示すAt配線と保護膜形成の工
程においてFi(なお、第2図におらて第1図に示した
部品表同じものは同一符号で示す)、先ずウェハ1の上
面全面にムL膜2′を蒸着しく(a))・続いて配線ツ
クターニングを通常の技術で行いAt配線2を形成しく
 (b) ) 、さらにウニ611面金@にアモルファ
スS1膜3′を嬉1図に示す実施例の場合と同様の方法
で堆積せしめる((・)〕0次いで、アモルファス81
属3′をAt配線2よ〕中中大きいノ9ターンでノ臂タ
ーニングしく (d) ) 、最後にウェハ表面金面に
PaG層4を成長させる・かかる工程を行って、At配
線2の上面と両側面は2重の保護膜で保−されることK
なす、耐食性は著しく向上するものである。
That is, in the process of forming the At wiring and protective film shown in FIG. The L film 2' is deposited (a)), and then the At wiring 2 is formed by wiring turning using a normal technique (b)), and then the amorphous S1 film 3' is deposited on the gold surface of the 611 surface. The amorphous 81 was deposited in the same manner as in the example shown in
(d)) Finally, grow a PaG layer 4 on the gold surface of the wafer surface. and both sides shall be protected by a double protective film.
As a result, corrosion resistance is significantly improved.

かかるアモルファスS1膜の鰺成は、ムtとクエ^  
  。
The formation of such an amorphous S1 film is based on Mut and Que^
.

表面との電気的接続を良好にするために行う熱処理(シ
ンタリング)中K A4表面に発生する突起を抑える効
果を有し、特にこの突起がP8G保護膜を傷つけ、腐食
の原因となることを考慮すれば、かかる効果の意義は大
なるものがあり、さらには直接外気にふれるIンディン
グペット部の保護膜としても利用できるものである。な
おアモルファスS1の抵抗を下げる必要のあるときに#
f通常の技術で不純物のドーピングを行う。
It has the effect of suppressing protrusions that occur on the K A4 surface during heat treatment (sintering) performed to improve electrical connection with the surface, and in particular prevents these protrusions from damaging the P8G protective film and causing corrosion. When taken into consideration, this effect has great significance, and furthermore, it can be used as a protective film for the inboard pet portion that is directly exposed to the outside air. In addition, when it is necessary to lower the resistance of amorphous S1, #
f Doping with impurities is performed using conventional techniques.

本発明は、上記したようにアモルファスs1を利用して
、At配線とP2O層との間に発生した従来技術の問題
点を解決するだけでなく、At配線はアモルファス81
膜とP2O層の2重構造によって保護されるので、本発
明に従う半導体装置はその信頼性が向上せしめられるも
のである。
The present invention utilizes amorphous s1 as described above to not only solve the problems of the prior art that occurred between the At wiring and the P2O layer, but also to solve the problems of the prior art between the At wiring and the P2O layer.
Since the semiconductor device according to the present invention is protected by the double structure of the film and the P2O layer, its reliability is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図とllN2図は、本発明の半導体装置を形成する
工11におけるアルミニウム配線の要部を一部断面で示
す斜視図である。 l・・・ウェハ、2・・・アルミニウム配線、2′・・
・アルミニウムl[,3,3’・・・アモルファス81
 j[,4・・・P2O層。 第1図 (e) 第2図
FIG. 1 and FIG. 1N2 are perspective views, partially in cross section, of essential parts of aluminum wiring in process 11 for forming the semiconductor device of the present invention. l...Wafer, 2...Aluminum wiring, 2'...
・Aluminum l[,3,3'...Amorphous 81
j[,4...P2O layer. Figure 1 (e) Figure 2

Claims (1)

【特許請求の範囲】[Claims] アルミニウム配線上にりん・シリケート′・ガラス層が
形成された半導体装置において、該アルミニウム配線の
少なくとも上面の上にアモルファスシリコン膜が形成さ
れ、該アモルファスシリコン膜上に前記りん・シリケー
ト・ガラス層が形成されたことを特徴とする半導体装置
In a semiconductor device in which a phosphorus/silicate/glass layer is formed on an aluminum wiring, an amorphous silicon film is formed on at least the upper surface of the aluminum wiring, and the phosphorus/silicate/glass layer is formed on the amorphous silicon film. A semiconductor device characterized by:
JP10288081A 1981-06-30 1981-06-30 Semiconductor device Pending JPS584948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10288081A JPS584948A (en) 1981-06-30 1981-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10288081A JPS584948A (en) 1981-06-30 1981-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS584948A true JPS584948A (en) 1983-01-12

Family

ID=14339185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10288081A Pending JPS584948A (en) 1981-06-30 1981-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS584948A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388845A (en) * 1986-10-01 1988-04-19 Nec Corp Manufacture of semiconductor device
JPS6387833U (en) * 1986-11-27 1988-06-08
JPS63147345A (en) * 1986-12-11 1988-06-20 Nec Corp Semiconductor integrated circuit device and manufacture thereof
JPH02170433A (en) * 1988-12-22 1990-07-02 Sony Corp Semiconductor device
JPH0346331A (en) * 1989-07-14 1991-02-27 Oki Electric Ind Co Ltd Formation of wiring pattern
EP0608335A1 (en) * 1991-10-11 1994-08-03 Vlsi Technology, Inc. Structure for suppression of field inversion caused by charge build-up in the dielectric

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984788A (en) * 1972-11-29 1974-08-14
JPS5023583A (en) * 1973-06-29 1975-03-13
JPS54145488A (en) * 1979-03-01 1979-11-13 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984788A (en) * 1972-11-29 1974-08-14
JPS5023583A (en) * 1973-06-29 1975-03-13
JPS54145488A (en) * 1979-03-01 1979-11-13 Toshiba Corp Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388845A (en) * 1986-10-01 1988-04-19 Nec Corp Manufacture of semiconductor device
JPS6387833U (en) * 1986-11-27 1988-06-08
JPS63147345A (en) * 1986-12-11 1988-06-20 Nec Corp Semiconductor integrated circuit device and manufacture thereof
JPH02170433A (en) * 1988-12-22 1990-07-02 Sony Corp Semiconductor device
JPH0346331A (en) * 1989-07-14 1991-02-27 Oki Electric Ind Co Ltd Formation of wiring pattern
EP0608335A1 (en) * 1991-10-11 1994-08-03 Vlsi Technology, Inc. Structure for suppression of field inversion caused by charge build-up in the dielectric
EP0608335A4 (en) * 1991-10-11 1994-11-17 Vlsi Technology Inc Structure for suppression of field inversion caused by charge build-up in the dielectric.

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