JPS58137233A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve flatness of surface and humidity proof characteristic of semiconductor element by stacking a low concentration phosphorus film on a high phosphorus concentration PSG film. CONSTITUTION:A silicon oxide film 2 and gate electrode 3 are formed on a silicon substrate 1. A high phosphorus concentration PSG film 8 is formed thereon at the entire part by the CVD method in the thickness of 5,000-10,000Angstrom . Next, the element surface is flatened by annealing under the nitrogen N2 ambient for about 10-50min at a temperature of 900-1,050 deg.C and a PSG film 9 in the phosphorus concentration of 1-2mol% is formed thereon by the CVD method at the entire part in the thickness of 1,000-2,000Angstrom . This film 9 may be a silicon oxide film or silicon nitride film not including phosphorus. After contact holes 5a are formed at the desired areas in the same way as the conventional example, the Al wiring 6 is formed, it is connected to a gate electrode 3 and a protection film 7 is formed at the entire part.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and includes Il! fK relates to the structure of the passivation film.

Conventionally, phosphosilicate glass (phosphor 8111cate G) has been used as a passivation film for semiconductor devices.
1ass+P8G)l[ is often used. FIG. 1 is a cross-sectional view showing the state 1!1 at the main stage of the manufacturing process for explaining a conventional configuration example of FiA~0.First, as shown in FIG. After the silicon oxide film (2) and the gate electrode (3) are formed, a PEG film (4) is formed on the entire upper surface thereof. This PEG
The film (4) is refrozen by heat treatment at about 1000° C. to flatten the surface of the element, and the phosphorus serves to prevent sodium ions and the like from entering the silicon oxide film (2). After reflowing by heat treatment and forming contact holes (6) at desired locations as shown in FIG. 1B, a metal wiring (6) made of aluminum or the like is formed and connected to the gate electrode (3). After that, Figure 1C
As shown in Figure 1, a protective film (7) (e.g. CVD
(silicon oxide film or silicon nitride film) is formed at low temperature.

However, it is known that in addition to the resin material and molding method of the semiconductor device thus obtained, the concentration of phosphorus contained in the passivation film of the element has a large influence. In other words, if water enters from the outside through the resin and further enters through a pinhole in the protective film (7) or a portion where the protective film (7) is not present (such as a not-shown bonding pad) and comes into contact with the PEG film (4). It reacts with phosphorus contained in the P2O film (4) to form phosphoric acid, which corrodes the aluminum wiring (6), causing disconnection and discoloration.

The phosphorus phenomenon ij: is promoted as the phosphorus concentration in the PsG film (4) increases.

However, as mentioned above, a phosphorus concentration above a certain level is required in order to flatten the surface of one element and prevent contamination such as sodium □Ja). The currently known conditions are:
In order to obtain surface flattening, a phosphorus concentration of at least 5 moles of vc Fi is required, and in order to maintain moisture resistance above a certain standard, it must be less than 5 moles.

This invention was made in view of the above points, and by overlapping a low phosphorus concentration film on high phosphorus concentration P8GllO, it is possible to flatten the element surface and improve moisture resistance. The purpose of this research is to provide a structure for a semiconductor device.

FIGS. 2A to 2D are cross-sectional views showing the main stages of the manufacturing process for explaining the configuration of an embodiment of the present invention. First, as shown in FIG. A silicon oxide film (2) and a gate electrode (3) are formed on the substrate 11), and a PsG film (8) with a cylindrical phosphorus concentration (approximately 8 to 9 molt) is deposited on the entire surface using the CVD method.
000 to 10,000 amps.

Next, after flattening the surface of the element by performing seven annealing operations in a Sm nitrogen (N2) atmosphere at a temperature of 900 to 1050°C to 100°C, as shown in FIG.
A PBG film (9) of about 2-t-k% was deposited by CVD to 10
It is formed on the entire surface to a thickness of 00 to 2000A. This film (9
) may be a silicon oxide film or a silicon nitride film that does not contain phosphorus. As shown in FIG. 2C and D, contact holes (5a) are formed at required locations in the same way as before, and then a gate electrode (3) is formed by forming a multilayer wiring (button).
1k l! (Form 71.

In the semiconductor device obtained by K in this way, the element surface is flattened by the high phosphorus concentration of P8GmlB+.
Low phosphorus concentration on top of that! ! The improvement in moisture resistance can be measured by +91.

In addition, the contact hole is formed using carbon tetrafluoride (O1').
4) can be carried out continuously in a plasma atmosphere.

The present invention is applicable to semiconductors other than silicon, and is effective when applied to any semiconductor element where flattening of the surface and improvement of moisture resistance of metal wiring is required.

As explained above, in the semiconductor device according to the present invention, the passivation film has a two-layer structure consisting of a lower layer made of a PEIG film with a high phosphorus concentration and an upper layer made of an insulating film with a low phosphorus concentration or no phosphorus. It is possible to improve moisture resistance while ensuring flatness.

[Brief explanation of the drawing]

Figures 1 A to 0 are cross-sectional views showing the main stages of the manufacturing process for explaining a conventional configuration example, and Figure 2 A
-D is a cross-sectional view showing the main stages of the manufacturing process for explaining the configuration of an embodiment of the present invention. In the figure, (1) is a silicon (semiconductor) base, (3)
(8) is an electrode, (8) is a P2O film with a high phosphorus concentration, (9) is a PSGik with a low phosphorus concentration, (5a) is a contact hole, and (the button is a metal wiring. Note that the same symbols in the figures indicate the same or corresponding parts. 0 Figure 1 Figure 2

Claims (1)

[Claims] +11 An electrode is provided on the surface of a semiconductor substrate, and a passivation film is provided covering the semiconductor substrate including the top of the electrode, and the metal wiring formed on the passivation film is connected to the passivation film. The passivation group is configured to be connected to the electrode through a contact hole provided in the film, and the passivation group includes a lower layer made of a phosphosilicate glass group with a high phosphorus concentration and an insulating layer with a low phosphorus concentration or without containing phosphorus. Semiconductor device 0 (2) characterized in that it has a two-layer structure 1 with an upper layer consisting of a film.The lower layer of the passivation film has a phosphorus concentration of 5 molar or more,
2. The semiconductor device according to claim 1, wherein the semiconductor device is made of silicic acid glass. (3) The semiconductor device according to claim 8 (1) or Fi (2), wherein the upper layer of the passivation film is a phosphosilicate glass film having an η concentration of δ mole or less. (4) The semiconductor device according to claim 1 or 2, wherein the upper layer of the passivation film is a silicon oxide film that does not contain phosphorus. (6) Claim 1, characterized in that the upper layer of the passivation film is a silicon nitride film that does not contain phosphorus.
3. The semiconductor device according to item 1 or 2.