JPS6356704B2 - - Google Patents
Info
- Publication number
- JPS6356704B2 JPS6356704B2 JP56084758A JP8475881A JPS6356704B2 JP S6356704 B2 JPS6356704 B2 JP S6356704B2 JP 56084758 A JP56084758 A JP 56084758A JP 8475881 A JP8475881 A JP 8475881A JP S6356704 B2 JPS6356704 B2 JP S6356704B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon nitride
- nitride layer
- low
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000002844 melting Methods 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 11
- 230000008018 melting Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000005360 phosphosilicate glass Substances 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 229910020617 PbO—B2O3—SiO2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の表面保護に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to surface protection of semiconductor devices.
半導体装置の電気的特性は外部からの不純物、
水分の影響で変動しやすく、また、アルミニウム
配線の用いられた装置では水分の侵入によつてア
ルミニウムが腐食されることが問題となる。この
ため、一般に、半導体装置の表面保護膜として二
酸化シリコン層あるいはリンシリケートガラス層
が用いられている。また、これらの保護膜では水
分の侵入に対する効果が小さいので、さらに耐湿
性を向上させるために、この保護膜上の構造のち
密な窒化シリコン層を形成した構造のものも作ら
れている。ところが、二酸化シリコン層あるいは
リンシリケートガラス層上に窒化シリコン層を形
成した場合、窒化シリコンは二酸化シリコンある
いはリンシリケートガラスに比べて熱膨脹率が非
常に大きいため、窒化シリコン成長時にその下の
層との界面に歪みが生じるので、温度変化に伴つ
て窒化シリコン層に微小なクラツクがはいり、こ
のクラツクから内部に水分が侵入するという現象
が発生しやすい。 The electrical characteristics of semiconductor devices are affected by external impurities,
It easily fluctuates due to the influence of moisture, and in devices using aluminum wiring, there is a problem that the aluminum corrodes due to moisture intrusion. For this reason, a silicon dioxide layer or a phosphosilicate glass layer is generally used as a surface protective film of a semiconductor device. Furthermore, since these protective films have little effect on moisture intrusion, in order to further improve the moisture resistance, structures have been made in which a dense silicon nitride layer is formed on the protective film. However, when a silicon nitride layer is formed on a silicon dioxide layer or a phosphosilicate glass layer, silicon nitride has a much larger coefficient of thermal expansion than silicon dioxide or phosphosilicate glass, so when the silicon nitride is grown, there is a problem with the layer below it. Since distortion occurs at the interface, minute cracks appear in the silicon nitride layer as the temperature changes, and moisture tends to enter the interior through these cracks.
本発明は半導体装置の保護膜として窒化シリコ
ン層を用いた時に生ずる上記欠点を取り除くもの
である。すなわち、半導体装置の形成された半導
体基板表面に、この半導体装置に用いられた各物
質の融点よりも低い温度で軟化する絶縁物質層
（以下、低温軟化絶縁物質層と呼ぶ）を形成し、
この低温軟化絶縁物質層の上に窒化シリコン層を
形成し、その時あるいはその後低温軟化絶縁物質
層だけを軟化させる温度で熱処理することによつ
て低温軟化絶縁物質層を軟化させ、窒化シリコン
層とその下の低温軟化絶縁物質層間に生じた歪み
を吸収させることで、温度変化に伴つて発生する
窒化シリコン膜のクラツクをなくそうというもの
である。 The present invention eliminates the above drawbacks that occur when a silicon nitride layer is used as a protective film for a semiconductor device. That is, an insulating material layer that softens at a temperature lower than the melting point of each substance used in the semiconductor device (hereinafter referred to as a low-temperature softening insulating material layer) is formed on the surface of a semiconductor substrate on which a semiconductor device is formed;
A silicon nitride layer is formed on the low-temperature softening insulating material layer, and the low-temperature softening insulating material layer is softened at that time or thereafter by heat treatment at a temperature that softens only the low-temperature softening insulating material layer, and the silicon nitride layer and the silicon nitride layer are softened. The idea is to eliminate cracks in the silicon nitride film that occur with temperature changes by absorbing the strain that occurs between the underlying low-temperature softening insulating material layers.
以下、実施例にもとづいて本発明を詳細に説明
する。 Hereinafter, the present invention will be explained in detail based on Examples.
第１図は従来の半導体装置の一例を示す部分断
面図である。第１図で、半導体基板１の表面に拡
散層２が形成されており、二酸化シリコン層３に
開けられた穴を介してアルミ配線４が拡散層２と
コンタクトをとつている。さらに、第１図ではア
ルミ配線４又は二酸化シリコン層３の上に、外部
から侵入してくる水又は不純物に対する保護膜と
して、リンシリケートガラス層５とその上に窒化
シリコン層６が形成されている。この窒化シリコ
ン層６をプラズマ窒化膜成長により300℃程度の
低温で形成しても、窒化シリコンの熱膨脹率がリ
ンシリケートガラスの熱膨脹率の10倍程度である
ため、窒化膜成長後常温に戻した時、窒化シリコ
ン層６とリンシリケートガラス層５との界面には
大きな歪みが発生する。そのため、温度変化又は
時間の経過に伴つて窒化シリコン層６にクラツク
が発生しやすくなつている。窒化シリコン層６に
クラツクが発生すると、その下に形成されている
リンシリケートガラス層がたやすく水分を通過さ
せてしまうので、外部からはいつてきた水分はク
ラツクを通つてアルミ配線４に到達し、アルミを
腐食し、ついには断線に至らしめる。 FIG. 1 is a partial cross-sectional view showing an example of a conventional semiconductor device. In FIG. 1, a diffusion layer 2 is formed on the surface of a semiconductor substrate 1, and an aluminum wiring 4 is in contact with the diffusion layer 2 through a hole made in a silicon dioxide layer 3. Furthermore, in FIG. 1, a phosphosilicate glass layer 5 and a silicon nitride layer 6 are formed on the aluminum wiring 4 or the silicon dioxide layer 3 as a protective film against water or impurities entering from the outside. . Even if this silicon nitride layer 6 is formed by plasma nitride film growth at a low temperature of about 300°C, the thermal expansion coefficient of silicon nitride is about 10 times that of phosphosilicate glass, so the temperature was returned to room temperature after the nitride film growth. At this time, a large strain occurs at the interface between the silicon nitride layer 6 and the phosphosilicate glass layer 5. Therefore, cracks are likely to occur in the silicon nitride layer 6 as the temperature changes or as time passes. If a crack occurs in the silicon nitride layer 6, the phosphosilicate glass layer formed underneath it will easily allow moisture to pass through, so the moisture coming in from the outside will pass through the crack and reach the aluminum wiring 4. , corrodes the aluminum and eventually leads to wire breakage.
そこで、窒化シリコン層６のクラツク発生の原
因となる窒化シリコン層６とその下の層との界面
に発生する歪みを少なくするために、本発明では
窒化シリコン層６とリンシリケートガラス層５の
間に低温軟化絶縁物質層を形成した。第２図が本
発明の一実施例である。第２図の構造は窒化シリ
コン層６とリンシリケートガラス層５の間に低温
軟化物質としてPbO−B2O3−SiO2系の低融点ガ
ラス層７が形成されている以外は第１図と同じで
ある。PbO−B2O3−SiO2系の低融点ガラス層７
の融点は300℃程度（例えばPbO：B2O3：SiO2＝
87：12：１の組成の場合その軟化点は290℃であ
る）なので、窒化シリコン層６の成長中あるいは
成長後300℃程度の熱処理を行なえば、アルミ配
線４をとかさずに低融点ガラス層７を軟化させる
ことができる。軟化した低融点ガラス層７は窒化
シリコン層６形成時に発生する歪みを吸収してし
まうため常温に戻したとき、低融点ガラス層７と
窒化シリコン層６との界面に発生する歪みは非常
に小さくなつている。 Therefore, in order to reduce the strain occurring at the interface between the silicon nitride layer 6 and the layer below it, which causes cracks in the silicon nitride layer 6, in the present invention, the gap between the silicon nitride layer 6 and the phosphosilicate glass layer 5 is A low-temperature softening insulating material layer was formed. FIG. 2 shows an embodiment of the present invention. The structure shown in FIG. 2 is the same as that shown in FIG. 1 except that a PbO-B 2 O 3 -SiO 2 -based low-melting glass layer 7 is formed as a low-temperature softening substance between the silicon nitride layer 6 and the phosphosilicate glass layer 5. It's the same. PbO−B 2 O 3 −SiO 2 based low melting point glass layer 7
The melting point of is about 300℃ (for example, PbO:B 2 O 3 :SiO 2
(In the case of a composition of 87:12:1, its softening point is 290°C). Therefore, if heat treatment is performed at about 300°C during or after the growth of the silicon nitride layer 6, it is possible to form a low melting point glass without melting the aluminum wiring 4. Layer 7 can be softened. The softened low melting point glass layer 7 absorbs the strain that occurs during the formation of the silicon nitride layer 6, so when the temperature is returned to room temperature, the strain that occurs at the interface between the low melting point glass layer 7 and the silicon nitride layer 6 is very small. It's summery.
従つて、本発明によれば保護膜として用いた窒
化シリコン層にクラツクがはいりにくいため耐湿
性にすぐれ信頼性の高い半導体装置が得られる。 Therefore, according to the present invention, cracks are less likely to occur in the silicon nitride layer used as a protective film, so that a semiconductor device with excellent moisture resistance and high reliability can be obtained.
なお、前記実施例における低融点ガラス層７は
CVD法またはガラスの粉末を溶剤にとかしたも
のを塗布した後乾燥する方法のいずれを用いても
容易に形成することができる。 In addition, the low melting point glass layer 7 in the above embodiment is
It can be easily formed using either the CVD method or a method in which a solution of glass powder dissolved in a solvent is applied and then dried.
また、前記低融点ガラス層の代わりに低温度で
軟化する樹脂などを用いても本発明の効果を上げ
ることができる。 Furthermore, the effects of the present invention can be enhanced by using a resin that softens at low temperatures instead of the low melting point glass layer.
第１図は従来の窒化シリコン層を保護膜として
用いた半導体装置の拡散層とアルミ配線のコンタ
クト部分の断面図、第２図は本発明の一実施例を
示す断面図である。
１……半導体基板、２……拡散層、３……二酸
化シリコン層、４……アルミ配線、５……リンシ
リケートガラス層、６……窒化シリコン層、７…
…低融点ガラス層。
FIG. 1 is a sectional view of a contact portion between a diffusion layer and an aluminum wiring of a semiconductor device using a conventional silicon nitride layer as a protective film, and FIG. 2 is a sectional view showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffusion layer, 3... Silicon dioxide layer, 4... Aluminum wiring, 5... Phosphorsilicate glass layer, 6... Silicon nitride layer, 7...
...Low melting point glass layer.
Claims (1)
記配線を含む前記基板上に絶縁層を有し、前記絶
縁層上に表面保護用の窒化シリコン層を有する半
導体装置において、前記窒化シリコン層と前記絶
縁層の間にアルミニウムの融点よりも低い温度で
軟化するガラス層または樹脂層を形成せしめたこ
とを特徴とする半導体装置。1. In a semiconductor device having an aluminum wiring on a semiconductor substrate, an insulating layer on the substrate including the wiring, and a silicon nitride layer for surface protection on the insulating layer, the silicon nitride layer and the insulating A semiconductor device characterized in that a glass layer or a resin layer that softens at a temperature lower than the melting point of aluminum is formed between the layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56084758A JPS57199224A (en) | 1981-06-02 | 1981-06-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56084758A JPS57199224A (en) | 1981-06-02 | 1981-06-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57199224A JPS57199224A (en) | 1982-12-07 |
| JPS6356704B2 true JPS6356704B2 (en) | 1988-11-09 |
Family
ID=13839577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56084758A Granted JPS57199224A (en) | 1981-06-02 | 1981-06-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57199224A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2625839B1 (en) * | 1988-01-13 | 1991-04-26 | Sgs Thomson Microelectronics | PROCESS FOR PASSIVATING AN INTEGRATED CIRCUIT |
| US6514882B2 (en) * | 2001-02-19 | 2003-02-04 | Applied Materials, Inc. | Aggregate dielectric layer to reduce nitride consumption |
| JP2006043813A (en) * | 2004-08-04 | 2006-02-16 | Denso Corp | Micro-system structure with protective film and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5390869A (en) * | 1977-01-21 | 1978-08-10 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5632732A (en) * | 1979-08-27 | 1981-04-02 | Mitsubishi Electric Corp | Semiconductor device |
-
1981
- 1981-06-02 JP JP56084758A patent/JPS57199224A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5390869A (en) * | 1977-01-21 | 1978-08-10 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5632732A (en) * | 1979-08-27 | 1981-04-02 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57199224A (en) | 1982-12-07 |
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