JPH0621229A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0621229A JPH0621229A JP17412592A JP17412592A JPH0621229A JP H0621229 A JPH0621229 A JP H0621229A JP 17412592 A JP17412592 A JP 17412592A JP 17412592 A JP17412592 A JP 17412592A JP H0621229 A JPH0621229 A JP H0621229A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- surface protective
- region
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の構造及び
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device structure and manufacturing method.
【0002】[0002]
【従来の技術】従来の半導体装置の構造を、図2に示
す。図2において半導体装置の表面保護膜は二層構造か
らなる。2. Description of the Related Art The structure of a conventional semiconductor device is shown in FIG. In FIG. 2, the surface protection film of the semiconductor device has a two-layer structure.
【0003】表面保護膜が複数層より構成される半導体
装置において、その内部配線を外部へ接続する部分であ
るところの電極形成領域Aとヒューズ開孔部形成領域B
での表面保護膜6、及び7の除去は一つの工程で同時に
行われ、電極形成領域Aとヒューズ開孔部形成領域Bで
表面保護膜6、及び7の全層が除去される。このためヒ
ューズ開孔部形成領域Bでは、半導体装置内部の層間絶
縁膜4が外気雰囲気に露出する構造をもつ。また、この
際、層間絶縁膜4の表面が少量除去され、層間絶縁膜4
の削れ部分Xが生じる。なお、図2において、符号1は
半導体装置基板、符号2は層間絶縁膜、符号3は半導体
装置内部配線、5は金属配線である。In a semiconductor device having a surface protective film composed of a plurality of layers, an electrode forming region A and a fuse opening forming region B, which are portions for connecting the internal wiring to the outside,
The removal of the surface protection films 6 and 7 is simultaneously performed in one step, and all the layers of the surface protection films 6 and 7 are removed in the electrode formation region A and the fuse opening portion formation region B. Therefore, in the fuse opening portion formation region B, the interlayer insulating film 4 inside the semiconductor device is exposed to the outside air atmosphere. At this time, a small amount of the surface of the interlayer insulating film 4 is removed, and the interlayer insulating film 4 is removed.
The scraped portion X of In FIG. 2, reference numeral 1 is a semiconductor device substrate, reference numeral 2 is an interlayer insulating film, reference numeral 3 is a semiconductor device internal wiring, and 5 is a metal wiring.
【0004】[0004]
【発明が解決しようとする課題】このような構造をもつ
従来の半導体装置は、ヒューズ開孔部形成領域Bでは表
面保護膜6、7の除去工程によって、半導体装置内部の
層間絶縁膜4が直接外気雰囲気に露出してしまうこと、
及び、上記の除去工程によるところの膜エッチングが層
間絶縁膜4の一部に達しその部分を除去し、層間絶縁膜
4の削れXを生じせしめ、層間絶縁膜4の外気雰囲気へ
の露出面積を増大せしめることから、金属配線5と、層
間絶縁膜4を浸透した外気雰囲気との化学反応による金
属配線5の腐食の発生頻度が増大し、金属配線5の耐湿
性を劣化させる等の問題があった。また、層間絶縁膜4
の材質に、BPSGのように吸湿性が高く、外気雰囲気
と金属配線5の化学反応を助長するような不純物を多く
含有する物を用いた場合、金属配線5の腐食の発生頻度
は更に増大し、問題はいっそう深刻化する。 そこで本
発明はこのような問題点を解決するものであり、その目
的とするところは、ヒューズ開孔部形成領域Bにおいて
少なくとも表面保護膜の最下層膜6の一層を除去せず、
半導体装置の耐湿性の向上をはかる半導体装置の表面保
護膜の構造及びその製造方法を提供するところにある。In the conventional semiconductor device having such a structure, in the fuse opening forming region B, the interlayer insulating film 4 inside the semiconductor device is directly removed by the step of removing the surface protective films 6 and 7. Exposure to the atmosphere,
Further, the film etching in the above removing step reaches a part of the interlayer insulating film 4 and removes the part to cause the scraping X of the interlayer insulating film 4 to increase the exposed area of the interlayer insulating film 4 to the atmosphere. Since the metal wiring 5 is increased, the frequency of corrosion of the metal wiring 5 due to the chemical reaction between the metal wiring 5 and the outside air atmosphere that has penetrated the interlayer insulating film 4 is increased, and there is a problem that the moisture resistance of the metal wiring 5 is deteriorated. It was In addition, the interlayer insulating film 4
When a material having a high hygroscopic property such as BPSG and containing a large amount of impurities that promotes a chemical reaction between the outside air atmosphere and the metal wiring 5 is used as the material of, the frequency of corrosion of the metal wiring 5 is further increased. , The problem gets worse. Therefore, the present invention solves such a problem, and an object thereof is to remove at least one lowermost layer film 6 of the surface protective film in the fuse opening forming region B,
It is an object of the present invention to provide a structure of a surface protective film of a semiconductor device and a method for manufacturing the same for improving the moisture resistance of the semiconductor device.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置は、
表面保護膜が二層以上の複数膜よりなり、電極形成領域
では保護膜が全層除去され金属配線の外部電極への接続
面は外気雰囲気に露出しており、一方、ヒューズ開孔部
形成領域では少なくとも表面保護膜最下層膜は除去され
ず層を形成しており層間絶縁膜は外気雰囲気に露出して
いない構造をもつことを特徴とする。The semiconductor device of the present invention comprises:
The surface protective film consists of two or more layers, and the entire protective film is removed in the electrode formation area, and the connection surface of the metal wiring to the external electrode is exposed to the outside air atmosphere. Is characterized in that at least the lowermost layer of the surface protective film is not removed and a layer is formed, and the interlayer insulating film has a structure not exposed to the outside air atmosphere.
【0006】本発明の半導体装置の製造方法は、まず半
導体装置の表面保護膜を二層以上の複数層積層し、表面
保護膜の少なくとも最下層一層を残して、上方の膜を電
極形成領域とヒューズ開孔部形成領域の2領域において
除去し、上記では除去されない下層膜を電極形成領域の
1領域においてのみ除去する工程を具備することを特徴
とする。According to the method of manufacturing a semiconductor device of the present invention, first, two or more surface protection films of a semiconductor device are laminated, and at least one lowermost layer of the surface protection film is left, and the upper film is used as an electrode formation region. The method is characterized by including a step of removing the lower layer film which is not removed in the above two areas of the fuse opening portion forming area and only one area of the electrode forming area.
【0007】あるいは、半導体装置の表面保護膜の下部
を構成する数層を積層し、この下部層を電極形成領域の
1領域においてのみ除去し、表面保護膜の上部を構成す
る数層を積層し、上記において形成された上部表面保護
膜を電極形成領域と、ヒューズ開孔部形成領域の2領域
において除去する工程を具備することを特徴とする。Alternatively, several layers constituting the lower part of the surface protective film of the semiconductor device are laminated, the lower layer is removed only in one region of the electrode forming region, and several layers constituting the upper part of the surface protective film are laminated. The method further comprises the step of removing the upper surface protective film formed above in two regions of the electrode formation region and the fuse opening portion formation region.
【0008】[0008]
【作用】本発明は表面保護膜下層膜が、ヒューズ開孔部
形成領域において除去されずに、なお一層を形成してい
るため、半導体装置内部の層間絶縁膜が外気雰囲気に露
出することがなく、また、上記従来技術の半導体装置の
構造における層間絶縁膜の削れが生じることもなく、層
間絶縁膜を浸透した外気雰囲気中の水分による金属配線
の腐食の発生頻度を低減する作用がある。According to the present invention, since the lower layer film of the surface protective film is not removed in the fuse opening portion forming region but is formed as a single layer, the interlayer insulating film inside the semiconductor device is not exposed to the outside air atmosphere. Further, the interlayer insulating film in the structure of the semiconductor device of the above-mentioned conventional technique is not scraped, and it has an effect of reducing the frequency of occurrence of corrosion of metal wiring due to moisture in the outside air atmosphere that has penetrated the interlayer insulating film.
【0009】[0009]
【実施例】以下、本発明の実施例を図面を用いて具体的
に説明する。Embodiments of the present invention will be specifically described below with reference to the drawings.
【0010】(実施例1)図1は本発明の一実施例を示
す、半導体装置の表面保護膜の断面図である。図1にお
いて半導体装置の表面保護膜は下層膜6、上層膜7の二
層で構成されている。なお図中に示された符号は図2と
一致する。(Embodiment 1) FIG. 1 is a sectional view of a surface protective film of a semiconductor device showing an embodiment of the present invention. In FIG. 1, the surface protective film of the semiconductor device is composed of two layers, a lower layer film 6 and an upper layer film 7. The reference numerals shown in the figure correspond to those in FIG.
【0011】電極形成領域Aでは、表面保護膜の下層膜
1、上層膜2の二層が除去されており金属配線5の外部
電極と接続される面は外気雰囲気に露出しているが、ヒ
ューズ開孔部形成領域Bでは上層膜7のみの除去であ
り、下層膜6は除去されずに保護膜を形成しており層間
絶縁膜4は外気雰囲気に露出していない構造をもつ。In the electrode forming region A, the lower layer film 1 and the upper layer film 2 of the surface protective film are removed, and the surface of the metal wiring 5 connected to the external electrode is exposed to the outside air atmosphere. In the opening portion forming region B, only the upper layer film 7 is removed, the lower layer film 6 is not removed and a protective film is formed, and the interlayer insulating film 4 has a structure not exposed to the outside air atmosphere.
【0012】次に本発明半導体装置の製造方法の実施例
についてのべる。Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
【0013】(a) 半導体装置の基板上に層間絶縁膜
2を酸化シリコンの、化学的気相成長法によるところの
デポジションにより、100nmの膜厚で形成される。(A) An interlayer insulating film 2 is formed on a substrate of a semiconductor device to a thickness of 100 nm by deposition of silicon oxide by a chemical vapor deposition method.
【0014】(b) 半導体装置の内部配線3をポリシ
リコン膜の100nmのデポジションによる積層、フォ
トリソグラフィ、エッチングにより形成する。(B) The internal wiring 3 of the semiconductor device is formed by laminating a polysilicon film by 100 nm deposition, photolithography, and etching.
【0015】(c) この上部に層間絶縁膜4がリン9
mol、ホウソ9molを不純物として含有するBPS
Gの化学的気相生長法によるデポジションにより800
nmの膜厚で形成される。(C) Interlayer insulating film 4 is formed on top of this by phosphorus 9.
mol and BPS containing boroso 9 mol as impurities
800 by G chemical vapor deposition
It is formed with a film thickness of nm.
【0016】(e) この層間絶縁膜7の上面に金属配
線5がアルミニウムの500nmのスパッタリング、フ
ォトリソグラフィ、エッチングにより形成される。(E) The metal wiring 5 is formed on the upper surface of the interlayer insulating film 7 by 500 nm sputtering of aluminum, photolithography, and etching.
【0017】(f) 半導体装置の表面保護膜の下層膜
6を酸化シリコンの化学的気相生長法による膜厚100
nmのデポジションにより形成する。(F) The lower layer film 6 of the surface protection film of the semiconductor device is formed to have a film thickness of 100 by the chemical vapor deposition method of silicon oxide.
nm deposition.
【0018】(g) 半導体装置の表面保護膜の上層膜
7を窒化珪素の化学的気相生長法による膜厚1000n
mのデポジションにより形成する。(G) The upper layer film 7 of the surface protective film of the semiconductor device is formed to a film thickness of 1000 n by the chemical vapor deposition method of silicon nitride.
It is formed by the deposition of m.
【0019】(h) 電極形成領域A上、及びヒューズ
開孔部形成領域B上の2ヶ所に開孔部のパターンを有す
るフォトリソグラフィ、エッチングにより半導体装置の
表面保護膜の上層膜7を除去する。(H) The upper layer film 7 of the surface protective film of the semiconductor device is removed by photolithography and etching having a pattern of openings on the electrode forming area A and on the fuse opening forming area B. .
【0020】(i) 電極形成領域A上の1ヶ所のみに
開孔部のパターンを有するフォトリソグラフィ、エッチ
ングにより半導体装置の表面保護膜の下層膜6を除去し
本発明の半導体装置の表面保護膜の構造を構成する。(I) The underlayer film 6 of the surface protection film of the semiconductor device is removed by photolithography or etching having a pattern of openings at only one place on the electrode formation region A to remove the surface protection film of the semiconductor device of the present invention. Constitutes the structure of.
【0021】(実施例2)本発明の半導体装置の製造方
法の実施例についてのべる。(Embodiment 2) An embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
【0022】上記実施例1中の工程(a)から(e)の
後、上記実施例1とは異なる以下の4工程により本発明
の半導体装置の表面保護膜の構造を構成する。After the steps (a) to (e) in the first embodiment, the structure of the surface protective film of the semiconductor device of the present invention is constituted by the following four steps different from the first embodiment.
【0023】(j) 半導体装置の表面保護膜の下層膜
6を酸化シリコンの化学的気相生長法による膜厚100
nmのデポジションにより形成する。(J) The lower layer film 6 of the surface protection film of the semiconductor device is formed to have a film thickness of 100 by the chemical vapor deposition method of silicon oxide.
nm deposition.
【0024】(k) 電極形成領域A上の1ヶ所のみに
開孔部のパターンを有するフォトリソグラフィ、エッチ
ングにより半導体装置の表面保護膜の下層膜6を除去す
る。(K) The lower layer film 6 of the surface protective film of the semiconductor device is removed by photolithography and etching having a pattern of openings at only one place on the electrode forming region A.
【0025】(l) 半導体装置の表面保護膜の上層膜
7を窒化珪素の化学的気相生長法による膜厚1000n
mのデポジションにより形成する。(L) The upper film 7 of the surface protection film of the semiconductor device is formed to have a film thickness of 1000 n by the chemical vapor deposition method of silicon nitride.
It is formed by the deposition of m.
【0026】(m) 電極形成領域A上、及びヒューズ
開孔部形成領域B上の2ヶ所に開孔部のパターンを有す
るフォトリソグラフィ、エッチングにより半導体装置の
表面保護膜の上層膜7を除去し本発明の半導体装置の表
面保護膜の構造を構成する。(M) The upper layer film 7 of the surface protection film of the semiconductor device is removed by photolithography and etching having a pattern of openings on the electrode forming area A and on the fuse opening forming area B. The structure of the surface protective film of the semiconductor device of the present invention is constituted.
【0027】[0027]
【発明の効果】以上述べたように、本発明の半導体装置
によれば、ヒューズ開孔部形成領域Bにおいて、表面保
護膜の下層膜6が除去されず、半導体装置内部の層間絶
縁膜4が外部雰囲気に露出せず、また、従来の半導体装
置に見られるような、層間絶縁膜4の削れが生じないこ
とにより、金属配線5の、外気雰囲気からの腐食の発生
頻度を低減することの効果がある。As described above, according to the semiconductor device of the present invention, the lower layer film 6 of the surface protective film is not removed in the fuse opening forming region B, and the interlayer insulating film 4 inside the semiconductor device is not removed. The effect of reducing the frequency of occurrence of corrosion of the metal wiring 5 from the outside atmosphere by not being exposed to the outside atmosphere and causing no abrasion of the interlayer insulating film 4 as seen in the conventional semiconductor device. There is.
【図1】本発明の半導体装置の表面保護膜の一実施例を
示す断面図。FIG. 1 is a sectional view showing an example of a surface protective film of a semiconductor device of the present invention.
【図2】従来の半導体装置の表面保護膜の構造を示す断
面図。FIG. 2 is a sectional view showing a structure of a surface protective film of a conventional semiconductor device.
1 半導体装置基板 2 層間絶縁膜 3 半導体装置内部配線 4 層間絶縁膜 5 金属配線 6 半導体装置の表面保護膜の下層膜 7 半導体装置の表面保護膜の上層膜 A 電極形成領域 B ヒューズ開孔部形成領域 X 層間絶縁膜4の削れ部分 1 Semiconductor Device Substrate 2 Interlayer Insulation Film 3 Semiconductor Device Internal Wiring 4 Interlayer Insulation Film 5 Metal Wiring 6 Lower Layer Film of Surface Protective Film of Semiconductor Device 7 Upper Layer Film of Surface Protective Film of Semiconductor Device A Electrode Forming Area B Fuse Opening Formation Area X The scraped portion of the interlayer insulating film 4
Claims (3)
り、内部配線を、表面保護膜の一領域が取り除かれた部
分を通して外部よりレーザー光により切断しうる領域
(ヒューズ開孔部形成領域)を有する半導体装置におい
て、 前記ヒューズ開孔部形成領域は、少なくとも前記表面保
護膜の最下層一層を有し、 かつ半導体装置の内部配線を外部に接続する電極形成領
域においては、表面保護膜の全層が除去されている構造
からなることを特徴とする半導体装置。1. The surface protective film is composed of a plurality of layers of two or more layers, and the internal wiring can be cut by a laser beam from the outside through a portion where one region of the surface protective film is removed (formation of a fuse opening portion). Region), the fuse opening formation region has at least one lowermost layer of the surface protection film, and the surface protection film is formed in the electrode formation region for connecting the internal wiring of the semiconductor device to the outside. A semiconductor device having a structure in which all the layers are removed.
数層積層する工程と、 表面保護膜の少なくとも最下層一層を残して、上方の膜
を電極形成領域とヒューズ開孔部形成領域の2領域にお
いて除去する工程、 上記の工程では除去されない下層膜を電極形成領域の1
領域においてのみ除去する工程を具備することを特徴と
する半導体装置の製造方法。2. A step of laminating two or more layers of a surface protective film of a semiconductor device, and an upper film of an electrode forming region and a fuse opening forming region leaving at least one lowermost layer of the surface protective film. 2 step of removing the lower layer film which is not removed in the above step in the electrode forming area
A method of manufacturing a semiconductor device, comprising the step of removing only in a region.
る数層を積層する工程と、この下部層を電極形成領域の
1領域においてのみ除去する工程と、 表面保護膜の上部を構成する数層を積層する工程と、 前記工程において形成された上部表面保護膜を電極形成
領域と、ヒューズ開孔部形成領域の2領域において除去
する工程を具備することを特徴とする半導体装置の製造
方法。3. A step of laminating several layers constituting a lower portion of a surface protective film of a semiconductor device, a step of removing the lower layer only in one region of an electrode forming region, and a number of constituting the upper portion of the surface protective film. A method of manufacturing a semiconductor device, comprising: a step of stacking layers; and a step of removing the upper surface protective film formed in the step in two regions of an electrode forming region and a fuse opening forming region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17412592A JPH0621229A (en) | 1992-07-01 | 1992-07-01 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17412592A JPH0621229A (en) | 1992-07-01 | 1992-07-01 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0621229A true JPH0621229A (en) | 1994-01-28 |
Family
ID=15973096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17412592A Pending JPH0621229A (en) | 1992-07-01 | 1992-07-01 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0621229A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09139384A (en) * | 1995-11-15 | 1997-05-27 | Nec Corp | Semiconductor device |
US5653265A (en) * | 1984-02-13 | 1997-08-05 | Excell Corporation | Hollow plastic product |
-
1992
- 1992-07-01 JP JP17412592A patent/JPH0621229A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5653265A (en) * | 1984-02-13 | 1997-08-05 | Excell Corporation | Hollow plastic product |
JPH09139384A (en) * | 1995-11-15 | 1997-05-27 | Nec Corp | Semiconductor device |
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