JPH05304268A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress a curve of a fin of a storage electrode relating to a semiconductor device having a fin-shaped stacked capacitor. CONSTITUTION:This semiconductor device composed including a first electrode of a fin construction formed of the films 11, 13, 15 for electrode forming to be composed by inserting at least one part of the intermediate layers 11b, 13b, 15b having the larger strength than the upper and lower conductive films 11a, 11c, 13a, 13c, 15a, 15c, and a dielectric film formed on the surface of the first electrode and a capacitor composed of a second electrode covering the dielectric film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a stacked capacitor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a stacked capacitor type DRAM cell, the area occupied by each cell tends to decrease as the degree of integration increases, but in order to prevent the storage capacity of the capacitor from decreasing, the storage electrode of the capacitor is It has been proposed to secure a wide surface area as a fin type structure.

Further, when the degree of integration is improved, it is possible to increase the number of fins of the storage electrode as a measure for reducing the size of the storage electrode. Therefore, next, a process of forming a storage electrode having three fins will be described with reference to FIG.

First, as shown in FIG. 7A, an interlayer insulating film 73 is laminated on a semiconductor substrate 72 on which a diffusion layer 71 of one conductivity type is formed, and a SiN film 74 and a SiO ₂ film are formed thereon. 75 are laminated, and _two polycrystalline silicon films 76 and _two SiO ₂ films 77 are alternately formed.

Then, the uppermost SiO ₂ film 77 above the diffusion layer 71 to the interlayer insulating film 73 are formed by photolithography.
After forming a contact hole 78 by opening up to (FIG. 7B), a third-layer polycrystalline silicon film 79 is formed on the entire surface (FIG. 7C).

After that, the third-layer polycrystalline silicon film 79 is formed.
The first to the first-layer polycrystalline silicon film 76 are patterned by photolithography, and these films are left only in the diffusion electrode 71 and the storage electrode formation region defined by the periphery thereof (FIG. 7D).

Then, by selectively removing the SiO ₂ films 75 and 77 above and below the polycrystalline silicon films 76 and 77 using hydrofluoric acid, the polycrystalline silicon film 7 is formed above the SiN film 74.
The fins 6 and 79 remain and serve as storage electrodes (FIG. 7E).

After this, although not particularly shown, the storage electrode 8
A dielectric film is formed along the surface of 0 by the CVD method, and a counter electrode made of polycrystalline silicon is further formed on the dielectric film to complete the capacitor.

In such a capacitor having a storage electrode, if the number of fins is simply increased, the height of the storage electrode 80 is increased, and the groove partitioning the storage electrode 80 is suddenly deepened. Processing becomes difficult. further,
The height difference between the capacitor region and the other regions becomes large, and it becomes difficult to form a pattern of the counter electrode extending over a plurality of cells and the aluminum wiring electrode above it from the viewpoint of the depth of focus of photoresist exposure.

Therefore, it is important to make the number of fins large while suppressing the height of the storage electrode, and for that purpose, it is effective to reduce the interval between the facing fins.

[0011]

However, when the distance between the opposing fins is reduced, there is a problem that the fins are likely to bend as shown in FIG. Note that the mechanism of curvature generation has not been clarified at this stage.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing the curvature of the fin of the storage electrode of the capacitor and a method of manufacturing the same.

[0013]

[Means for Solving the Problems]
4, the upper and lower conductive films 11a, 11c, 13a, 13c, 15
a, 15c the intermediate layer 11b, 13b, 13b, 15b having a greater strength than the first electrode 21 of the fin structure formed by the electrode forming film 11, 13, 15, which is inserted in at least a portion, and the first The dielectric film 22 formed on the surface of the electrode 21 of the
It is achieved by a semiconductor device characterized in that it has a capacitor constituted by a second electrode 23 that covers the.

Alternatively, the step of forming the impurity diffusion layer 7 of the opposite conductivity type in the semiconductor substrate 1 of the one conductivity type, the step of laminating the first insulating film 9 on the semiconductor substrate 1, directly or On the first insulating film 9 via the second insulating film 10,
First electrode forming films 11 and 13 and third insulating films 12 and 14 formed by inserting intermediate layers 11b, 13b and 15b) having high mechanical strength
And at least one layer alternately, a step of patterning the film above the impurity diffusion layer 7 to form the opening 17, and a mechanical strength on the uppermost third insulating film 13 Forming a second electrode forming film 15 having a large intermediate layer 15b therein along the inside of the opening 17 and the surface of the uppermost third insulating film 14, and at least forming the second electrode Film 15 to the first electrode forming film 1
By patterning the layers up to 1 and 13, the first electrode forming films 11 and 13 and the second electrode forming film 15 are formed into the openings.
The first electrode for the capacitor left on 17 and its surroundings
21; a step of selectively removing the second insulating film 10 and the third insulating films 12 and 14 on the first insulating film 9 with an etching solution; Forming a dielectric film 22 for the capacitor around the electrode 21,
A second electrode for the capacitor is provided around the dielectric film 22.
And a step of forming 23. This is achieved by a method for manufacturing a semiconductor device.

Alternatively, the intermediate films 11b, 13b, 15b) are insulators or conductors that are not etched when the second insulating film 10 and the third insulating films 12, 14 are selectively removed,
Alternatively, the second insulating film 10 and the third insulating films 12 and 13
It is achieved by a method for manufacturing a semiconductor device, which is characterized by being formed of an insulator or a conductor having an etching rate lower than that of the above.

[0016]

[Operation] According to the present invention, in a capacitor having a fin-shaped storage electrode (first electrode) 21, the fin portion of the storage electrode 21 has an intermediate film 11b,
Inserted 13b and 15b.

Therefore, since the strength of the fin as a whole is increased, the fin of the storage electrode 21 is not curved during the process of forming the capacitor. In addition, the intermediate films 11b, 13b,
Since 15b is for preventing the fin of the storage electrode 21 from being curved, it is important that it remains after the insulating films 10, 12, and 14 around the storage electrode 21 are etched, and is not etched during this etching. Alternatively, it is necessary to select a material with a low degree of etching.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment Device of the Present Invention FIGS. 1 and 2 are sectional views showing the first embodiment of the present invention, FIG.
4 is a sectional view showing the main part thereof.

In FIG. 1A, reference numeral 1 is a p-type semiconductor substrate made of silicon. On the upper surface of the semiconductor substrate 1, a SiO ₂ field oxide film 2 surrounding the active region X is formed to a thickness of 400 nm by a selective oxidation method. It is formed to a thickness.

In this state, first, on the upper surface of the semiconductor substrate 1 in the active region X, the gate insulating film 3 of SiO ₂ having a thickness of about 10 nm is formed.
Are formed by a thermal oxidation method, and then a polycrystalline silicon film 4 having a thickness of 100 nm is grown by CVD, and phosphorus is introduced to reduce the resistance of the polycrystalline silicon film 4.

Next, as shown in FIG. 1B, the polycrystalline silicon film 4 is patterned by using the photolithography technique, and thereby the word line 5 passing through the active region X and the field oxide film 2 is formed. Then, using the word lines 5 in the active region X as a mask, phosphorus is ion-implanted into the semiconductor substrate 1 on both sides of the mask, whereby n for source / drain is formed.
^{The +} type diffusion layers 6a, 6b and 7 are formed. Further, an interlayer insulating film 8 made of SiO ₂ is uniformly grown on the entire surface.

Next, by the photolithography method,
The interlayer insulating film 8 above the diffusion layer in the active region (not shown) is opened to form a contact hole, and then a bit line (not shown) passing therethrough is formed. The process up to this point is the same as the process of forming a conventional DRAM cell.

Thereafter, as shown in FIGS. 1 (c) and 3 (a), a silicon nitride film (SiN film) 9 is deposited to a thickness of about 50 nm, and then a SiO ₂ film 10 is deposited to a thickness of 50 nm. Further, the storage electrode film 11 including the polycrystalline silicon film 11a having a film thickness of 20 nm, the SiN film 11b having a film thickness of 10 nm, and the polycrystalline silicon film 11c having a film thickness of 20 nm is formed. In this way, the SiN film 9
After alternately laminating two layers of the SiO ₂ films 10 and 12 and the storage electrode films 11 and 13 on each of them, the SiO ₂ film 14 is 50 nm, the polycrystalline silicon layer 15a is 20 nm, and the SiN film 15b is 10 nm.
grow up. Note that these films grow by the CVD method.

After this, as shown in FIG. 3A, a photoresist 16 is applied, exposed and developed to form a window 16a above the diffusion layer 7 on the side not connected to the bit line. Then, the film located below the window 16a is removed by reactive etching to form an opening 17 as shown in FIG. 3 (b).
And the diffusion layer 7 is exposed.

Further, in the opening 17 and the uppermost SiN film 15
The polycrystalline silicon film 15c is formed along the line b by the CVD method.
Laminate about 0 nm. This polycrystalline silicon film 15c constitutes the storage electrode film 15 together with the underlying SiN 15b and the polycrystalline silicon film 15a.

After that, as shown in FIG. 3C, the opening 17 and the storage electrode forming region around the opening 17 are covered with the photoresist 19, and the film in the other region is covered with the first storage electrode film. Up to 11 are removed by reactive ion etching (FIG. 4 (d)).

Further, when hydrofluoric acid is supplied through the groove 20 formed by etching to thereby isotropically remove all the SiO ₂ films 10, 12, 14 above the SiN film 9 of the _first layer, the storage electrode The films 11, 13, and 15 are shown in FIG. 4 (e).
Since it remains in the shape of a fin as shown in (3), this is used as the storage electrode 21 of the capacitor.

After that, the capacitor insulating film 22 is grown by the CVD method or the like. Thus, since the SiN films 11b, 13b, 15b having a mechanical strength higher than that of polycrystalline silicon are inserted as an intermediate layer inside each fin constituting the storage electrode 21, the strength of the entire fin is increased. As a result, in the process from the hydrofluoric acid treatment for forming the storage electrode 21 to the growth of the dielectric film 22, the fin curvature did not occur.

After forming the dielectric film 22 as described above, as shown in FIG. 2D, a polycrystalline silicon film 23 is grown to a thickness of about 100 nm by the CVD method, and phosphorus is introduced by the thermal diffusion method. The polycrystalline silicon film 23 is reduced in resistance.

Then, the polycrystalline silicon film 23 is patterned to serve as a counter electrode, whereby the capacitor Q is completed. At this stage, since the gaps between the fins of the storage electrode 21 are completely filled, it is not necessary to consider the occurrence of the bending of the fins in the subsequent steps.

Further, as shown in FIG.
A flattening film 24 having a two-layer structure of O ₂ and BPSG is formed, an aluminum electrode wiring layer 25 is formed thereon, an interlayer insulating film 26 covering the electrode wiring layer 25 is further formed, and an aluminum wiring 27 is formed thereon. Is formed, and finally the cover film 28 is formed, whereby the DRAM cell is completed.

Further, in the above-mentioned embodiment, the two layers of storage electrode films 11 and 13 are formed, the polycrystalline silicon film 15a and the SiN film 15c are further formed thereon, and then the opening 17 is provided, and then the polycrystalline film is formed. Although the silicon film 18 is formed to support the fins, the two storage electrode films 11,
An opening 17 is provided immediately after forming 13, and then a storage electrode film of a third layer is formed in the opening 17 and along the SiO ₂ film 14, and the storage electrode film of the third layer is formed. You may make it support a fin by. (B) Description of the Second Embodiment of the Present Invention In the above-described embodiments, the SiN film 11 is used as an intermediate layer in the storage electrode films 11, 13 and 15 which form the fins of the storage electrode.
Although b and 13b are inserted, they may be formed of a SiO ₂ film or another insulating film.

Therefore, an embodiment in which a SiO ₂ film is interposed as an intermediate layer in the storage electrode film will be described below with reference to FIGS. 5 and 6. First, as shown in FIG. 5 (a), a PSG film 30 having a thickness of 50 nm is formed on the SiN film 9, and subsequently, a polycrystalline silicon film 31a having a film thickness of 20 nm and a film thickness of 10 nm are formed.
The SiO ₂ film 31b and the polycrystalline silicon film 31c having a thickness of 20 nm are sequentially laminated to form the storage electrode film 31. Further, in the same manner, the PSG film 32 and the storage electrode film 33 are formed.
Then, a SiO ₂ film 34 is grown to 50 nm, a polycrystalline silicon layer 35a is grown to 20 nm, and a SiN film 35b is grown to 10 nm. These films are grown by the CVD method.

After this, as shown in FIG. 5A, a photoresist 36 is applied, exposed and developed to form a window 36a above the diffusion layer 7 on the side not connected to the bit line. Then, the film below the window 36a is removed by reactive etching to form an opening 37 as shown in FIG. 5B, and the diffusion layer 7 is exposed.

Further, a polycrystalline silicon film 35c is laminated by the CVD method to a thickness of about 20 nm, and this film and the uppermost SiN film 3 are stacked.
5b, the polycrystalline silicon film 35a, and the storage electrode film 3
1 is formed, the opening 37 is formed as shown in FIG. 5 (c).
And the storage electrode formation region in the periphery of the photoresist 39
Then, the film in the exposed region is etched by reactive ion etching to remove the storage electrode film 31 up to the first layer (FIG. 6D).

Further, the groove 4 formed by etching
Hydrofluoric acid is supplied through 0, and the SiN film 9
When all of the PSG films 30, 32, 34 above the are removed isotropically, the storage electrode films 31, 33, 35 become
As shown in (e), since it remains in a fin shape, this is used as the storage electrode 40 of the capacitor.

In this case, the storage electrode films 31, 33, 35
The SiO ₂ films 31b, 33b, 35c, which are intermediate layers of the PSG films 30, 32, 34, are etched by hydrofluoric acid.
Since the etching rate for hydrofluoric acid is extremely smaller than that of the above, only the outer peripheral edge portion of the fin is removed, and the function of reinforcing the fin remains.

Further, the traces of the SiO ₂ films 31b, 33b, 35b removed show the polycrystalline silicon film 31 above and below it.
The peripheral portions of a, c, 33a, c, 35a, and c are in contact with each other so as to cover the remaining SiO ₂ films 31b, 33b, and 35b.

Thereafter, as shown in FIG. 6F, a dielectric film 41 is formed on the surface of the storage electrode 40 on the first-layer silicon nitride film 9 in the same manner as in the first embodiment. (C) Description of Other Embodiments of the Present Invention In the above-mentioned embodiments, the number of fins of the storage electrode is three, but the number of fins is not limited to this. The number of sheets may be four or more.

In the above embodiment, the intermediate layer of the storage electrode film is formed of an insulating material such as SiO ₂ or PSG. However, polycrystalline silicon having a large grain size or a conductive material such as tungsten or titanium is used. May be used.

[0041]

As described above, according to the present invention, in a capacitor having a storage electrode (first electrode) having a fin structure, the film forming the fin of the storage electrode has a large mechanical strength. Since the intermediate film is inserted, the strength of the fin as a whole is increased, and it is possible to prevent the fin from being bent in the capacitor forming process.

Further, the intermediate film is made of a material which is not etched or has a low etching rate when the insulating film around the storage electrode is etched, so that the fin of the storage electrode is surely prevented from bending. It

[Brief description of drawings]

FIG. 1 is a sectional view (1) showing a first embodiment of the present invention.

FIG. 2 is a sectional view (2) showing the first embodiment of the present invention.

FIG. 3 is a sectional view (No. 1) showing an essential part of the first embodiment of the present invention.

FIG. 4 is a sectional view (No. 2) showing a main part of the first embodiment of the present invention.

FIG. 5 is a sectional view (No. 1) showing a main part of a second embodiment of the present invention.

FIG. 6 is a sectional view (No. 2) showing a main part of the second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing an example of a conventional method.

FIG. 8 is a cross-sectional view showing a curved state of a conventional storage electrode.

[Explanation of symbols]

1 semiconductor substrate 2 field oxide film 3 gate insulating film 8 interlayer insulating film 9 SiN film 10, 12, 14 SiO ₂ film 11, 13, 15 electrode film 11a, 11c, 13a, 13c, 15a, 15c polycrystalline silicon film 11b , 13b, 15b SiN film 17 Opening 21 Storage electrode (first electrode) 22 Dielectric film 23 Counter electrode (second electrode) 30, 32, 34 PSG film 31, 33, 35 Electrode film 31a, 31c, 33a, 33c, 35a, 35c Polycrystalline silicon film 31b, 33b, 35b SiO ₂ film 37 Opening 41 Storage electrode (first electrode) 42 Dielectric film 43 Counter electrode (second electrode)

Claims (3)

[Claims] 1. Upper and lower conductive films (11a, 11c, 13a, 13c, 15a, 15c)
A first electrode (21) having a fin structure formed by an electrode forming film (11, 13, 15) in which at least a part of an intermediate layer (11b, 13b, 15b) having a higher strength than that is inserted, A capacitor having a dielectric film (22) formed on the surface of the first electrode (21) and a second electrode (23) covering the dielectric film (22), Semiconductor device. 2. A step of forming an impurity diffusion layer (7) of opposite conductivity type in a semiconductor substrate (1) of one conductivity type, and a first insulating film (9) on the semiconductor substrate (1). The step of laminating, and the intermediate layer (11b, 13b, 15) having large mechanical strength is directly or through the second insulating film (10) on the first insulating film (9).
First electrode formation film (11, 13) with b) inserted inside
And a third insulating film (12, 14) are alternately laminated at least one layer, and a film above the impurity diffusion layer (7) is patterned to form an opening (17). The second electrode forming film (15) having an intermediate layer (15b) having a large mechanical strength therein is formed on the third insulating film (13) in the opening (17) and the uppermost film. A step of forming along the surface of the third insulating film (14), and patterning at least the layers from the second electrode forming film (15) to the first electrode forming film (11, 13) And the first electrode forming film (11, 13) and the second electrode forming film (15) are left in the opening (17) and its periphery to form a first electrode (21) for a capacitor. ) And the second insulating film (10) on the first insulating film (9)
And a step of selectively removing the third insulating film (12, 14) with an etching solution, and a step of forming a dielectric film (22) for the capacitor around the first electrode (21) And a step of forming the second electrode (23) for the capacitor around the dielectric film (22). 3. The insulator (11b, 13b, 15b) which is not etched when the second insulating film (10) and the third insulating film (12, 14) are selectively removed. Or a conductor, or an insulator or a conductor having an etching rate smaller than that of the second insulating film (10) and the third insulating film (12, 13). Item 3. A method of manufacturing a semiconductor device according to item 2.