JPH0582511A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0582511A
JPH0582511A JP26697691A JP26697691A JPH0582511A JP H0582511 A JPH0582511 A JP H0582511A JP 26697691 A JP26697691 A JP 26697691A JP 26697691 A JP26697691 A JP 26697691A JP H0582511 A JPH0582511 A JP H0582511A
Authority
JP
Japan
Prior art keywords
insulating film
film
tip
final protective
field oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26697691A
Other languages
Japanese (ja)
Inventor
Hiroshi Aoki
浩 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP26697691A priority Critical patent/JPH0582511A/en
Publication of JPH0582511A publication Critical patent/JPH0582511A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the final protective film having an excellent film condition, and to provide a semiconductor device in which the safety of the inside semiconductor element can be protected. CONSTITUTION:After a field oxide film 12 has been formed on a semiconductor substrate 11, a lower layer insulating film 13 is formed with its tip slightly staggering from the field oxide film 12, an upper layer of insulating film 14 is formed thereon with its tip staggering from the tip of the lower layer of insulating film 13, and the final protective film 15 is formed thereon staggering its tip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、良好な最終保護膜の
被膜状態を得ることにより、内部素子を完全に保護する
ことができるようにした半導体素子およびその製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element capable of completely protecting an internal element by obtaining a good state of a final protective film, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、ウェハ内に複数のチップを製作す
る際には、チップの分割を行いやすいようにスクライブ
・ラインを形成するのが一般的である。このスクライブ
・ラインは、ゲート電極層と配線層は後にショート等を
引き起すことのないように除去し、絶縁膜層も、チップ
切り出し時にクラック等を発生させ、内部素子を劣化さ
せることのないよう、切り出しに必要な部分の除去を各
層のエッチング時に行う。
2. Description of the Related Art Conventionally, when a plurality of chips are manufactured in a wafer, it is common to form scribe lines so that the chips can be easily divided. This scribe line is removed so that the gate electrode layer and the wiring layer do not cause a short circuit later, and the insulating film layer also does not cause cracks or the like when the chip is cut out and deteriorate the internal elements. The portions necessary for cutting are removed at the time of etching each layer.

【0003】図2は従来の半導体素子の断面図である。
図中の21は半導体基板であり、この半導体基板21に
フィールド酸化膜22を形成した後、第1絶縁膜23,
第2フィールド酸化膜24を順次内側に位置するように
切り出しに必要な部分の除去をエッチングにより行って
形成した後、最終保護膜25を形成している。
FIG. 2 is a sectional view of a conventional semiconductor device.
Reference numeral 21 in the figure denotes a semiconductor substrate. After forming a field oxide film 22 on the semiconductor substrate 21, a first insulating film 23,
After the second field oxide film 24 is sequentially formed so as to be positioned on the inner side by removing the portion necessary for cutting out by etching, the final protective film 25 is formed.

【0004】この際、図2に示すように、第1の絶縁膜
23,第2の絶縁膜24の各絶縁層の先端を内側にずら
し、最終保護膜25を最も外側へ出し、チップ全体を覆
う構造とするのが普通である。
At this time, as shown in FIG. 2, the tips of the respective insulating layers of the first insulating film 23 and the second insulating film 24 are shifted inward, and the final protective film 25 is moved to the outermost side, so that the entire chip is formed. The structure is usually covered.

【0005】これは、各絶縁層の先端が揃った場合、図
3の円A1内に示すごとく、その段差26が急になり、
最終保護膜25が完全に被膜せず、ここより水分等が侵
入することにより、素子劣化を引き起すことを防止する
ためである。
This is because when the tips of the insulating layers are aligned, the step 26 becomes steep as shown in the circle A1 in FIG.
This is to prevent the final protective film 25 from being completely covered and causing deterioration of the device due to intrusion of water or the like from here.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図2に
示すような半導体素子の構造においては、上層の第2の
絶縁膜24をエッチング除去する際に、そのオーバエッ
チング時に下層の第1の絶縁膜23も除去されてしま
い、甚だしい場合は図4の円A2内に示すごとき段差を
生じ、図3の例と変わらない形状となり、満足のできる
最終保護膜25の被膜ができなかった。
However, in the structure of the semiconductor device as shown in FIG. 2, when the second insulating film 24 in the upper layer is removed by etching, the first insulating film in the lower layer is overetched. 23 was also removed, and in the extreme case, a step as shown in the circle A2 of FIG. 4 was generated, and the shape was the same as that of the example of FIG. 3, and a satisfactory final protective film 25 could not be formed.

【0007】これは、一般的に絶縁層は酸化膜、もしく
は、酸化膜に不純物(リン、ボロン等)をドープしたも
のであり、エッチング時の各絶縁膜と半導体基板21と
の選択比が十分に得られないことおよびスクライブ・ラ
インは数十〜数百μmにおよぶ広い領域であるため、エ
ッチングが内部より速く進むためである。
This is because the insulating layer is generally an oxide film or the oxide film is doped with impurities (phosphorus, boron, etc.), and the selection ratio between each insulating film and the semiconductor substrate 21 during etching is sufficient. This is because the scribe line is a wide region ranging from several tens to several hundreds of μm, and etching progresses faster than the inside.

【0008】請求項1の発明は前記従来技術が持ってい
る問題点のうち、スクライブ・ラインでの段差形状が悪
化することにより、最終保護膜の被膜状態が劣化すると
いう問題点について解決した半導体素子を提供するもの
である。
The invention of claim 1 solves the problem that the state of the final protective film is deteriorated due to the deterioration of the step shape at the scribe line among the problems of the prior art. An element is provided.

【0009】請求項2の発明は、前記従来技術が持って
いる問題点のうち、第1,第2の絶縁膜を形成する酸化
物に不純物をドーピングすることによるエッチング時の
選択比が十分にとれずエッチングが内部より速く進む点
について解決した半導体素子の製造方法を提供するもの
である。
According to the second aspect of the present invention, among the problems of the prior art, the selection ratio at the time of etching by doping the oxide forming the first and second insulating films with impurities is sufficient. The present invention provides a method for manufacturing a semiconductor device, which solves the problem that etching proceeds faster than inside.

【0010】[0010]

【課題を解決するための手段】請求項1の発明は、半導
体素子において、先端をずらして上層が下層を覆うよう
に複数層の絶縁膜を設けたものである。
According to a first aspect of the present invention, in a semiconductor element, a plurality of insulating films are provided so that the upper layer covers the lower layer by shifting the tip.

【0011】請求項2の発明は半導体素子の製造方法に
おいて、下層の絶縁膜上に上層の絶縁膜を形成する際に
先端をずらして下層の絶縁膜を上層の絶縁膜で完全に覆
う工程を導入したものである。
According to a second aspect of the present invention, in the method of manufacturing a semiconductor element, a step of shifting the tip to completely cover the lower insulating film with the upper insulating film when forming the upper insulating film on the lower insulating film is performed. It was introduced.

【0012】[0012]

【作用】請求項1の発明によれば、以上のように半導体
素子を構成したので、下層の絶縁膜が上層の絶縁膜を覆
うことにより、絶縁膜と基板の選択比が十分にとれ、エ
ッチング時のずれを生じなくなり、最終保護膜の被膜状
態が良好になり、したがって、前記問題を除去できる。
According to the invention of claim 1, since the semiconductor element is configured as described above, the lower insulating film covers the upper insulating film, so that a sufficient selection ratio between the insulating film and the substrate can be obtained, and etching can be performed. There is no time lag and the state of the final protective film is good, so that the above problems can be eliminated.

【0013】請求項2の発明によれば、半導体素子の製
造方法において、以上のような工程を導入したので、絶
縁膜と基板との選択が十分とれることになり、最終保護
膜を被覆してもカバーレッジがよくなる。
According to the second aspect of the present invention, since the steps as described above are introduced in the method of manufacturing a semiconductor element, the insulating film and the substrate can be sufficiently selected, and the final protective film is coated. Also has better coverage.

【0014】[0014]

【実施例】以下、この発明の半導体素子およびその製造
方法の実施例について図面に基づき説明する。図1はこ
の発明の製造方法によって得られたこの発明の半導体素
子の断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device of the present invention obtained by the manufacturing method of the present invention.

【0015】この図1に示すように、半導体基板11上
にフィールド酸化膜12を形成した後に、下層の第1絶
縁膜13を形成する。この第1絶縁膜13は下層のフィ
ールド酸化膜12より数μm外側に位置している。
As shown in FIG. 1, after the field oxide film 12 is formed on the semiconductor substrate 11, the lower first insulating film 13 is formed. The first insulating film 13 is located outside the lower field oxide film 12 by several μm.

【0016】この第1絶縁膜13上に第2の絶縁膜14
を形成する。この際、第2絶縁膜14は第1絶縁膜13
よりさらに数μm外側に位置する。
A second insulating film 14 is formed on the first insulating film 13.
To form. At this time, the second insulating film 14 is replaced by the first insulating film 13
It is located outside by several μm.

【0017】次いで、第2絶縁膜14上に最終保護膜1
5を形成するが、この最終保護膜15は全体を覆う構造
となっている。
Then, the final protective film 1 is formed on the second insulating film 14.
5 is formed, the final protective film 15 has a structure that covers the entire surface.

【0018】このような構造を採用することにより、最
終保護膜15を生成する際に、各絶縁層、すなわち、第
1絶縁膜13,第2絶縁膜14の先端が数μmづつずれ
ているため、なだらかな形状となり、図3で示した従来
の半導体素子のごとき段差とはならず、良好な被膜状態
が得られ、かつ、上層の第2絶縁膜14のエッチングの
際に、この第2絶縁膜14のエッチングが内部より速く
終っても、半導体基板11がエッチング雰囲気にさらさ
れるため、第2絶縁膜14とは高い選択比(約5倍程
度)が得られる。
By adopting such a structure, when the final protective film 15 is formed, the tips of the respective insulating layers, that is, the first insulating film 13 and the second insulating film 14 are displaced by several μm. , It has a gentle shape, does not have a step like the conventional semiconductor element shown in FIG. 3, a good film state is obtained, and the second insulating film 14 is formed when the upper second insulating film 14 is etched. Even if the etching of the film 14 is completed faster than the inside, the semiconductor substrate 11 is exposed to the etching atmosphere, so that a high selection ratio (about 5 times) with respect to the second insulating film 14 can be obtained.

【0019】このため、オーバエッチングによるいわゆ
るえぐれは生じず、図1のごとき形状となり、最終保護
膜の被膜状態を悪化させることはない。本実施例におい
ては、絶縁膜は2層構造となっているが、これに限定さ
れるものではなく、3層以上の絶縁膜から成っていて
も、各絶縁膜が順に下層膜を上層膜で覆う構造になって
いれば同様の効果を得ることが可能である。
For this reason, so-called hollowing due to overetching does not occur, and the shape as shown in FIG. 1 is obtained, and the coating state of the final protective film is not deteriorated. In the present embodiment, the insulating film has a two-layer structure, but the present invention is not limited to this, and even if the insulating film is composed of three or more layers, each insulating film is a lower layer film and an upper layer film in order. The same effect can be obtained if the structure is used.

【0020】[0020]

【発明の効果】以上、詳細に説明したように、請求項1
の発明によれば、上層の絶縁膜が下層の絶縁膜を覆うよ
うに先端をずらしてあるため、オーバエッチング時のエ
グレを引き起さず、常に良好な最終保護膜の被膜状態を
得ることが可能となる。したがって、水分等の侵入に強
い半導体素子の実現が可能となる。
As described above in detail, the first aspect of the present invention is provided.
According to the invention, since the upper insulating film is shifted in its tip so as to cover the lower insulating film, it is possible to always obtain a good film state of the final protective film without causing egress during overetching. It will be possible. Therefore, it is possible to realize a semiconductor element that is resistant to intrusion of water and the like.

【0021】請求項2の発明によれば、半導体基板上に
下層の絶縁膜を形成後上層の絶縁膜の先端をずらして形
成した後、最終保護膜を上層の絶縁膜上に先端をずらし
て形成するようにしたので、エッチングが基板と絶縁膜
との高い選択比に基づいて行われ、オーバエッチング時
のえぐれを引き起さず、常に良好な最終保護膜を得るこ
とができ、したがって、内部素子を完全に保護すること
ができる。
According to the second aspect of the present invention, after the lower insulating film is formed on the semiconductor substrate and the tip of the upper insulating film is shifted, the final protective film is shifted on the upper insulating film. Since it is formed, the etching is performed based on the high selection ratio between the substrate and the insulating film, and it is possible to always obtain a good final protective film without causing an undercut at the time of overetching. The element can be completely protected.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の半導体素子の一実施例の構成を示す
断面図。
FIG. 1 is a sectional view showing the configuration of an embodiment of a semiconductor device of the present invention.

【図2】従来の半導体素子の断面図。FIG. 2 is a sectional view of a conventional semiconductor device.

【図3】従来の半導体素子の各絶縁層のカバーレッジを
説明するための断面図。
FIG. 3 is a cross-sectional view for explaining the coverage of each insulating layer of a conventional semiconductor device.

【図4】従来の半導体素子の各絶縁層のカバーレッジを
説明するための断面図。
FIG. 4 is a cross-sectional view for explaining the coverage of each insulating layer of a conventional semiconductor element.

【符号の説明】[Explanation of symbols]

11 半導体基板 12 フィールド酸化膜 13 第1絶縁膜 14 第2絶縁膜 15 最終保護膜 11 semiconductor substrate 12 field oxide film 13 first insulating film 14 second insulating film 15 final protective film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上にフィールド酸化膜を介し
て形成され、このフィールド酸化膜の領域より外側に、
前記半導体基板と接する領域を有する下層の絶縁膜と、 前記下層の絶縁膜上に形成され、前記下層の絶縁膜の領
域より外側に、前記半導体基板と接する領域を有する上
層の絶縁膜と、 前記上層の絶縁膜上に形成され、前記上層の絶縁膜の領
域より外側に、前記半導体基板と接する領域を有する最
終保護膜と、 よりなる半導体素子。
1. A semiconductor device is formed on a semiconductor substrate via a field oxide film, and outside the region of the field oxide film,
A lower insulating film having a region in contact with the semiconductor substrate, and an upper insulating film having a region in contact with the semiconductor substrate, formed on the lower insulating film, outside the region of the lower insulating film, A semiconductor device comprising: a final protective film formed on an upper insulating film and having a region outside the region of the upper insulating film and in contact with the semiconductor substrate.
【請求項2】 半導体基板上にフィールド酸化膜を形成
した後、このフィールド酸化膜の先端より先端をずらし
て下層の絶縁膜を形成する工程と、 上記下層の絶縁膜上に、この下層の絶縁膜の先端より先
端をずらして上層の絶縁膜を形成する工程と、 上記上層の絶縁膜上に、この上層の絶縁膜の先端より先
端をずらして最終保護膜を形成する工程と、 よりなる半導体素子の製造方法。
2. A step of forming a field oxide film on a semiconductor substrate and then forming a lower insulating film by shifting the tip of the field oxide film from the tip of the field oxide film, and insulating the lower layer on the lower insulating film. A step of forming an upper insulating film by displacing the tip from the tip of the film, and a step of forming a final protective film on the upper insulating film by displacing the tip from the tip of the upper insulating film Manufacturing method of device.
JP26697691A 1991-09-19 1991-09-19 Semiconductor device and manufacture thereof Pending JPH0582511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26697691A JPH0582511A (en) 1991-09-19 1991-09-19 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26697691A JPH0582511A (en) 1991-09-19 1991-09-19 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0582511A true JPH0582511A (en) 1993-04-02

Family

ID=17438331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26697691A Pending JPH0582511A (en) 1991-09-19 1991-09-19 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0582511A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687320B2 (en) 2004-03-08 2010-03-30 Oki Semiconductor Co., Ltd. Manufacturing method for packaged semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687320B2 (en) 2004-03-08 2010-03-30 Oki Semiconductor Co., Ltd. Manufacturing method for packaged semiconductor device

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