KR100338956B1 - Method for forming pad region of semiconductor chip - Google Patents
Method for forming pad region of semiconductor chip Download PDFInfo
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- KR100338956B1 KR100338956B1 KR1020000039113A KR20000039113A KR100338956B1 KR 100338956 B1 KR100338956 B1 KR 100338956B1 KR 1020000039113 A KR1020000039113 A KR 1020000039113A KR 20000039113 A KR20000039113 A KR 20000039113A KR 100338956 B1 KR100338956 B1 KR 100338956B1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체칩의 패드영역 형성방법에 관한 것으로, 종래에는 패터닝된 금속층의 사이에 여전히 두꺼운 SOG막이 형성되어 있으므로, 마이크로-BGA 패키징시 패드영역의 필-오프를 방지하는데 한계를 갖는 문제점이 있었다. 따라서, 본 발명은 메모리셀 영역을 형성하기 위하여 진행되는 비아콘택 형성공정을 패드영역에 도입하여 종래 금속층의 이격된 영역에 두껍게 형성된 SOG막을 식각하고, 비아콘택을 형성하는 반도체칩의 패드영역 형성방법을 제공함으로써, 별도로 추가되는 공정없이 SOG막의 두께를 전체적으로 최소화할 수 있게 되어 패드영역의 필-오프를 효과적으로 방지할 수 있는 효과가 있다.The present invention relates to a method for forming a pad region of a semiconductor chip. In the related art, since a thick SOG film is still formed between the patterned metal layers, there is a problem in that the pad region is prevented from peeling off during micro-BGA packaging. . Therefore, in the present invention, a method of forming a pad region of a semiconductor chip in which a via contact forming process, which is performed to form a memory cell region, is introduced into a pad region to etch a thick SOG film formed in a spaced area of a conventional metal layer and form a via contact. By providing a, it is possible to minimize the thickness of the SOG film as a whole without a separate process, there is an effect that can effectively prevent the peel-off of the pad area.
Description
본 발명은 반도체칩의 패드영역 형성방법에 관한 것으로, 특히 마이크로-BGA 패키지시 금속층과 SOG(spin-on-glass)막의 경도차이에 의해 발생되는 패드영역의 필-오프(peel-off) 현상을 방지하기에 적당하도록 한 반도체칩의 패드영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pad region of a semiconductor chip. In particular, a peel-off phenomenon of a pad region caused by a difference in hardness between a metal layer and a spin-on-glass film in a micro-BGA package is disclosed. It relates to a method for forming a pad region of a semiconductor chip suitable for preventing.
일반적으로, 완성된 하나의 반도체칩은 데이터를 저장하는 메모리셀 영역, 데이터 처리를 위한 주변 회로영역 및 데이터 입출력을 위한 패드영역 등을 구비하는데, 상기 메모리셀 영역을 형성하는 동안에 주변 회로영역이나 패드영역도 자신의 영역에 요구되는 공정을 선택적으로 수용하여 하나의 웨이퍼 상에서 동시에 제조된다. 이때, 자신의 영역에 불필요한 공정들은 마스크를 형성하고, 그 공정이 완료된 후에 마스크를 제거함으로써, 해당 공정을 수용하지 않으며, 자신의 영역에 별다른 영향을 미치지 않는 공정들은 상기와 같은 공정 복잡화 및 해당 공정에 따른 다른 영역과의 평탄도 불량등을 방지하기 위하여 그대로 수용한다.In general, a completed semiconductor chip includes a memory cell region for storing data, a peripheral circuit region for data processing, a pad region for data input / output, and the like. The peripheral circuit region or pad is formed during the formation of the memory cell region. Regions are also fabricated simultaneously on one wafer, selectively accepting the processes required for their region. In this case, by removing the mask after the process is completed, masks that are unnecessary in their area do not accept the process, and processes that do not affect the area of the process are complicated as described above and the corresponding process. It is accommodated as it is to prevent poor flatness with other areas.
따라서, 메모리셀 영역이 형성되는 동안에 일반적인 반도체칩의 패드영역은 도1의 단면도에 도시한 바와같이 층간절연막(1) 상부에 순차적으로 SOG막(2), TEOS막(3)이 형성되고, 최종적으로 TEOS막(3) 상부에 데이터의 입출력을 위한 금속층(4)을 패터닝하여 형성된다.Therefore, while the memory cell region is formed, the SOG film 2 and the TEOS film 3 are sequentially formed over the interlayer insulating film 1 as shown in the cross-sectional view of FIG. 1. As a result, the metal layer 4 for inputting / outputting data is formed on the TEOS film 3.
그러나, 상기한 바와같은 일반적인 반도체칩의 패드영역은 후속 마이크로-BGA 패키지시 SOG막(2)과 금속층(4)의 경도차이로 인해 패드영역의 필-오프 현상이 발생되는 문제점이 있으며, 그 SOG막(2)의 두께가 두꺼울수록 그 현상이 심화된다는 보고가 있었다.However, the pad region of the general semiconductor chip as described above has a problem in that a peel-off phenomenon of the pad region occurs due to the difference in hardness between the SOG film 2 and the metal layer 4 in the subsequent micro-BGA package. It has been reported that the thicker the film 2 is, the worse the phenomenon becomes.
상기한 바와같은 패드영역의 필-오프를 방지하기 위하여 상기 SOG막(2)의 두께를 부분적으로 최소화하는 패드영역의 구조가 제안되었는데, 이를 첨부한 도2의 단면도를 참조하여 상세히 설명하면 다음과 같다.In order to prevent the peel-off of the pad region as described above, a structure of the pad region which partially minimizes the thickness of the SOG film 2 has been proposed, which will be described in detail with reference to the cross-sectional view of FIG. same.
칩의 패드영역 상에 형성되는 층간절연막(11)과; 상기 층간절연막(11)의 상부에 일정하게 이격 패터닝되는 금속층(12)과; 상기 층간절연막(11) 및 금속층(12)의 상부 전면에 형성되는 박막의 TEOS층(13)과; 상기 TEOS층(13)의 상부 전면에 형성되며, 상기 금속층(12)의 이격된 영역을 채워 평탄화시키는 SOG막(14)과; 상기 평탄화된 SOG막(14)의 상부에 형성되는 박막의 TEOS층(15)과; 상기 TEOS층(15)의 상부에 패터닝되는 상부금속층(16)으로 이루어진다.An interlayer insulating film 11 formed on the pad region of the chip; A metal layer 12 that is uniformly spaced apart on the interlayer insulating film 11; A thin film TEOS layer 13 formed on the entire upper surface of the interlayer insulating film 11 and the metal layer 12; An SOG film 14 formed on the entire upper surface of the TEOS layer 13 to fill and planarize the spaced areas of the metal layer 12; A thin film TEOS layer 15 formed on the planarized SOG film 14; The upper metal layer 16 is patterned on top of the TEOS layer 15.
상기 도2에 도시한 패드영역의 구조에서는 금속층(12)이 패터닝된 상부에서 SOG막(14)의 두께를 최소화함으로써, 마이크로-BGA 패키징시 SOG막(14)의 두께에 따라 SOG막(14)과 상부금속층(16)의 경도차이로 발생하는 패드영역의 필-오프를 방지하였다.In the structure of the pad region shown in FIG. 2, the SOG film 14 is minimized according to the thickness of the SOG film 14 during micro-BGA packaging by minimizing the thickness of the SOG film 14 on the patterned metal layer 12. The peel-off of the pad area caused by the difference in hardness between the upper metal layer 16 and the upper metal layer 16 is prevented.
그러나, 상기한 바와같은 종래 반도체칩의 패드영역은 패터닝된 금속층의 사이에 여전히 두꺼운 SOG막이 형성되어 있으므로, 마이크로-BGA 패키징시 패드영역의 필-오프를 방지하는데 한계를 갖는 문제점이 있었다.However, in the pad region of the conventional semiconductor chip as described above, since a thick SOG film is still formed between the patterned metal layers, there is a problem in that the pad region is prevented from peeling off during the micro-BGA packaging.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 메모리셀 영역을 형성하기 위하여 진행되는 비아콘택 형성공정을 도입하여 패드영역에 형성되는 SOG막의 두께를 전체적으로 최소화함으로써, 패드영역에서 발생하는 필-오프를 효과적으로 방지할 수 있는 반도체칩의 패드영역 형성방법을 제공하는데 있다.The present invention has been devised to solve the above-mentioned problems, and an object of the present invention is to minimize the thickness of the SOG film formed in the pad region by introducing a via contact forming process which is performed to form the memory cell region. The present invention provides a method for forming a pad region of a semiconductor chip which can effectively prevent peel-off occurring in the pad region.
도1은 종래 반도체칩 패드영역 구조의 일 예를 보인 단면도.1 is a cross-sectional view showing an example of a conventional semiconductor chip pad region structure.
도2는 종래 반도체칩 패드영역 구조의 다른 예를 보인 단면도.2 is a cross-sectional view showing another example of a conventional semiconductor chip pad region structure.
도3a 내지 도3f는 본 발명의 일 실시예를 보인 수순단면도.3A to 3F are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
21:층간절연막 22:식각방지막21: interlayer insulating film 22: etching prevention film
23,25,28:TEOS막 24,29:SOG막23,25,28: TEOS film 24,29: SOG film
26,30:비아콘택 27:금속층26,30: Via contact 27: Metal layer
31:상부금속층31: upper metal layer
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체칩의 패드영역 형성방법은 층간절연막이 형성된 반도체칩의 패드영역 상에 식각방지막을 형성한 다음 상부전면에 제1 절연막을 형성하는 공정과; 상기 제1 절연막의 상부에 제1 SOG막을 형성하여 평탄화한 다음 상부에 제2 절연막을 형성하는 공정과; 상기 식각방지막이 부분적으로 노출되도록 적층된 제2 절연막, 제1 SOG막 및 제1 절연막을 선택 식각하여 다수개의 이격 홀을 형성한 다음 그 홀내에 도전성물질을 채워 제1 비아콘택을 형성하는 공정과; 상기 제2 절연막 상부에 제1 비아콘택과 접속되는 금속층을 이격 패터닝한 다음 상부전면에 제3 절연막을 형성하고, 제2 SOG막을 금속층의 이격된 영역이 채워지도록 형성하여 평탄화하는 공정과; 상기 금속층의 이격된 영역 사이의 식각방지막이 노출되도록 적층된 제2 SOG막, 제3절연막, 제2 절연막, 제1 SOG막 및 제1 절연막을 식각하여 이격 홀을 형성한 다음 그 홀내에 도전성물질을 채워 제2 비아콘택을 형성하는 공정과; 상기 결과물의 상부전면에 상부금속층을 패터닝하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A method of forming a pad region of a semiconductor chip for achieving the object of the present invention as described above comprises the steps of: forming an etch stop layer on a pad region of a semiconductor chip on which an interlayer insulating film is formed, and then forming a first insulating film on the upper surface; Forming and planarizing a first SOG film on the first insulating film, and then forming a second insulating film on the first insulating film; Forming a plurality of spaced apart holes by selectively etching the second insulating film, the first SOG film, and the first insulating film stacked to partially expose the etch stop layer, and then filling the conductive material to form the first via contact; ; Patterning a metal layer connected to the first via contact on the second insulating layer, and then forming a third insulating layer on the upper surface of the second insulating layer, and forming a second SOG film to fill the spaced regions of the metal layer; The second SOG film, the third insulating film, the second insulating film, the first SOG film, and the first insulating film are etched so as to expose the etch stop layer between the spaced apart regions of the metal layer to form a spaced hole, and then a conductive material in the hole. Filling the gaps to form second via contacts; And a step of patterning the upper metal layer on the upper front surface of the resultant.
상기한 바와같은 본 발명에 의한 반도체칩의 패드영역 형성방법을 첨부한도3a 내지 도3e의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to FIG. 3A through FIG. 3E, the cross-sectional view of the procedure of forming a pad region of a semiconductor chip according to the present invention as described above is described in detail.
먼저, 도3a에 도시한 바와같이 층간절연막(21)이 형성된 반도체칩의 패드영역 상에 식각방지막(22)을 형성한다. 이때, 식각방지막(22)은 산화막 계열과의 식각선택비가 우수하여야 하며, 예를 들어 폴리실리콘, 폴리사이드(polycide) 또는 텅스텐층 중에 선택된 하나로 형성하는 것이 바람직하다.First, as shown in FIG. 3A, an etch stop layer 22 is formed on a pad region of a semiconductor chip on which the interlayer insulating layer 21 is formed. In this case, the etch stop layer 22 should have an excellent etching selectivity with respect to the oxide film series, for example, it is preferably formed of one selected from polysilicon, polycide, or tungsten.
그리고, 도3b에 도시한 바와같이 상기 식각방지막(22)의 상부에 순차적으로 TEOS막(23), SOG막(24) 및 TEOS막(25)을 형성한 다음 상기 식각방지막(22)이 부분적으로 노출되도록 선택 식각하여 다수개의 이격 홀을 형성하고, 그 홀내에 도전성물질을 채워 비아콘택(26)을 형성한다. 이때, 비아콘택(26)의 사이즈는 0.35㎛, 비아콘택(26)간 이격거리는 0.65∼0.85㎛ 정도로 형성하는 것이 바람직하다.3B, the TEOS film 23, the SOG film 24, and the TEOS film 25 are sequentially formed on the etch stop layer 22, and then the etch stop layer 22 is partially formed. Selective etching is performed to expose a plurality of spaced apart holes, and a via contact 26 is formed by filling a conductive material in the holes. In this case, the size of the via contact 26 is preferably 0.35 μm, and the separation distance between the via contacts 26 is about 0.65 to 0.85 μm.
그리고, 도3c에 도시한 바와같이 상기 TEOS막(25) 상부에 비아콘택(26)과 접속되는 금속층(27)을 이격 패터닝 한다. 이때, 금속층(27)은 1.0∼1.3㎛ 정도의 피치(pitch)를 갖도록 형성하는 것이 바람직하다.3C, the metal layer 27 connected to the via contact 26 is spaced apart on the TEOS layer 25. At this time, the metal layer 27 is preferably formed to have a pitch of about 1.0 to 1.3㎛.
그리고, 도3d에 도시한 바와같이 상기 금속층(27)을 포함하여 TEOS막(25) 상부전면에 순차적으로 TEOS막(28)과 SOG막(29)을 형성하여 금속층(27)의 이격된 영역이 채워지도록 평탄화한다.As shown in FIG. 3D, the TEOS film 28 and the SOG film 29 are sequentially formed on the upper surface of the TEOS film 25 including the metal layer 27 so that spaced apart regions of the metal layer 27 are formed. Flatten to fill.
그리고, 도3e에 도시한 바와같이 상기 금속층(27)의 이격된 영역 사이의 식각방지막(22)이 노출되도록 적층된 SOG막(29), TEOS막(28,25), SOG막(24) 및 TEOS막(23)을 식각하여 이격 홀을 형성한 다음 홀내에 도전성물질을 채워 비아콘택(30)을 형성한다. 이때, 비아콘택(30)은 0.35㎛ 정도의 사이즈로 형성하는 것이 바람직하다.As shown in FIG. 3E, the SOG film 29, the TEOS films 28 and 25, the SOG film 24, which are stacked so that the etch stop layer 22 between the spaced apart regions of the metal layer 27 are exposed. The TEOS layer 23 is etched to form a spaced hole, and then a via contact 30 is formed by filling a conductive material in the hole. At this time, the via contact 30 is preferably formed in a size of about 0.35㎛.
그리고, 도3f에 도시한 바와같이 상기 비아콘택(30)을 포함하여 SOG막(29) 상부전면에 상부금속층(31)을 패터닝한다.3F, the upper metal layer 31 is patterned on the top surface of the SOG film 29 including the via contact 30.
상기한 바와같은 본 발명에 의한 반도체칩의 패드영역 형성방법은 메모리셀 영역을 형성하기 위하여 진행되는 비아콘택 형성공정을 패드영역에 도입하여 종래 금속층의 이격된 영역에 두껍게 형성된 SOG막을 식각하고, 비아콘택을 형성함에 따라 별도로 추가되는 공정없이 SOG막의 두께를 전체적으로 최소화할 수 있게 되어 패드영역의 필-오프를 효과적으로 방지할 수 있는 효과가 있다.In the method of forming a pad region of a semiconductor chip according to the present invention as described above, a via contact forming process, which is performed to form a memory cell region, is introduced into a pad region to etch an SOG film thickly formed in a spaced region of a metal layer. By forming the contact, it is possible to minimize the thickness of the SOG film as a whole without any additional process, thereby effectively preventing the peel-off of the pad region.
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