JPS60202441A - Mask for forming pattern for semiconductor device - Google Patents

Mask for forming pattern for semiconductor device

Info

Publication number
JPS60202441A
JPS60202441A JP59061372A JP6137284A JPS60202441A JP S60202441 A JPS60202441 A JP S60202441A JP 59061372 A JP59061372 A JP 59061372A JP 6137284 A JP6137284 A JP 6137284A JP S60202441 A JPS60202441 A JP S60202441A
Authority
JP
Japan
Prior art keywords
film
mask
glass substrate
thickness
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59061372A
Other languages
Japanese (ja)
Other versions
JPH0366656B2 (en
Inventor
Yaichiro Watakabe
渡壁 弥一郎
Hiroaki Morimoto
森本 博明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59061372A priority Critical patent/JPS60202441A/en
Publication of JPS60202441A publication Critical patent/JPS60202441A/en
Publication of JPH0366656B2 publication Critical patent/JPH0366656B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/54Absorbers, e.g. of opaque materials

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

PURPOSE:To prompt etching speed and to obtain a fine pattern more easily by forming a silicide film of Mo, W, or Ta on a glass substrate directly or interposing a polysilicon film and using the silicide film for the pattern-forming mask. CONSTITUTION:After coating a polysilicon film 4 to 1,000Angstrom film thickness on a glass substrate 1 such as quartz, a silicide film 3 of Mo, W, or Ta is deposited thereon to ca.200Angstrom film thickness. A photoresist or an EB resist is coated thereon to ca.500Angstrom thickness, then a specified pattern is formed with light or EB. Thereafter, the silicide film 3 is developed and then etched. In this case, the etching is executed easily by a dry method.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体装置の製造に使用するパターン形成
マスクの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in pattern forming masks used in the manufacture of semiconductor devices.

〔従来技術〕[Prior art]

第1図は従来の半導体装置の製造に使用するパターン形
成マスクの被層状態を示すもので、この図において、1
は石英等からなる透明のガラス基板、2はクロム(C「
)等の金属薄膜で、これは蒸着またはスパッタリング法
により前記ガラス基板ている。
Figure 1 shows the layered state of a pattern forming mask used in the manufacture of conventional semiconductor devices.
2 is a transparent glass substrate made of quartz, etc., and 2 is a chromium (C'
), which is deposited on the glass substrate by vapor deposition or sputtering.

従来の半導体装置用パターン形成マスクは、上記のよう
にCrを使用したハードマスクが一般に使用されている
。しかしながら、このCrのウェットエツチングでは高
精度マスクの製造が困難であり、また、ドライエツチン
グでは高精度のものが得られるが、Crエツチング速度
が約】oo叉/ml口以下で能率が悪く、がっ、併用さ
れるレジストとの選択比も悪いため量産に適していなか
った。
As a conventional pattern forming mask for a semiconductor device, a hard mask using Cr as described above is generally used. However, with wet etching of Cr, it is difficult to manufacture a high-precision mask, and with dry etching, a high-precision mask can be obtained, but the Cr etching speed is less than about 10 mm/ml, making it inefficient. The selection ratio with the resist used in combination was also poor, making it unsuitable for mass production.

〔発明の概要〕[Summary of the invention]

この発明は、上記従来のものの欠点を除去するためにな
されたもので、具体的には石英等からなるガラス基板上
に直接またはポリシリコン膜を介L−C,モリフ7’ン
(Mo)またはタングステン(W)あるいはタンタル(
Ta )のシリサイド化膜を形成し、これをパターン形
成マスクとして使用することを特徴とするものである。
The present invention has been made to eliminate the drawbacks of the above-mentioned conventional ones. Specifically, it is possible to apply LC, molyphen (Mo) or Tungsten (W) or tantalum (
This method is characterized in that a silicided film of Ta) is formed and used as a pattern forming mask.

ところで、半導体装置の製造に使用されるパターン形成
マスクは、初期においてはガラス基板を用いた写真乳剤
乾板を利用していたが、高集積化。
By the way, the pattern forming masks used in the manufacture of semiconductor devices initially used photographic emulsion dry plates with glass substrates, but with the advent of higher integration.

微細化が進むにつれて、現在ではガラス基板上にCr等
の金属薄膜からなる1、いわゆる八−ドマスクが広く使
用されている。このようなCr等の金属薄膜は蒸層また
はスパッタリング法により約6υUA7よいLliUU
Aj’J腺厚に形成され、七〇皮要ノマスク化には、こ
の金属薄膜上に7オトレジストまたは電子ビーム(EB
)用レジスト等を適宜塗布した後、これに光またはEB
により所要のパターンを描画した後、現像、エツチング
等の工程を経て作られる。
As miniaturization progresses, a so-called eight-domain mask made of a thin film of metal such as Cr on a glass substrate is now widely used. Such a metal thin film such as Cr can be formed by a vapor layer or sputtering method to form a thin film of about 6υUA7.
The metal thin film is formed to have a thickness of Aj'J, and to make a mask of about 70mm, photoresist or electron beam (EB) is applied on this thin metal film.
) After applying a suitable resist etc., it is exposed to light or EB.
After drawing the required pattern, it is created through processes such as development and etching.

なお、この除のエツチングは金属薄膜がCrの場合、ウ
ェット法では硝酸第二セリウムアンモンと過塩素酸で行
い、また、ドライ法では四塩化炭素(CCI、)と酸素
(02)の混合ガスで行うが、半導体装置が特にVLS
I等のように高集積化。
In addition, when the metal thin film is Cr, this etching is performed using ceric ammonium nitrate and perchloric acid in the wet method, or with a mixed gas of carbon tetrachloride (CCI) and oxygen (02) in the dry method. However, semiconductor devices are especially suitable for VLS
Highly integrated like I etc.

微細パターンを有する場合にはドライエツチング法が有
利であることが知られている。以下、この発明について
説明する@ 〔発明の実施例〕 第2図はこの発明の一実施例を示すもので、この図にお
いて、1は石英等からなる透明のガラス基板、3はスパ
ッタリング法等で形成したモリクテン(Mo )または
タングステン(W)あるいはタンタル(Ta )のシリ
サイド化膜であり、その膜厚な500人ないし1tlU
(IA牲茨の薄膜に形成する場合には、特にI CB 
(Ionized Cruster Beam)法で行
えば高精度のものが得られる。
It is known that dry etching is advantageous when a fine pattern is formed. This invention will be explained below. [Embodiment of the Invention] Figure 2 shows an embodiment of the invention. In this figure, 1 is a transparent glass substrate made of quartz or the like, and 3 is a transparent glass substrate made of quartz or the like. It is a silicided film of molyctene (Mo), tungsten (W), or tantalum (Ta) formed, and the film thickness is 500 to 1 tlU.
(When forming a thin film of IA sacrificial thorn, especially ICB
(Ionized Cluster Beam) method provides high accuracy.

上記のようにして、ガラス基板1上罠被看させたシリサ
イド化膜3上にフォトレジストまたはEBレジストを約
500A程度の厚さに塗布した後、光またはEBで所定
のパターンを描画する。その後、現像処理を経て当該シ
リサイド化膜3のエツチングを行う。この場合のエツチ
ングはドライ法で容易に行える。
As described above, a photoresist or EB resist is applied to a thickness of about 500 Å on the silicided film 3 placed on the glass substrate 1, and then a predetermined pattern is drawn with light or EB. Thereafter, the silicided film 3 is etched through a development process. Etching in this case can be easily performed using a dry method.

具体的には、Moのシリサイド化膜3の場合にはCF、
+O,(2%)の混合ガスを使用し、0.2Torrの
真空度とし、300Wの条件下でエツチングを行うと約
100 OA/ minのエツチングスピードで所期の
加工が終了する。このエツチングスピードは、従来のC
rのドライエツチングスピードに比べ約1/10になっ
ている。
Specifically, in the case of the Mo silicide film 3, CF,
When etching is performed using a mixed gas of +O, (2%) at a vacuum level of 0.2 Torr and under conditions of 300 W, the desired processing is completed at an etching speed of about 100 OA/min. This etching speed is higher than that of conventional C
The dry etching speed is about 1/10 of that of r.

以上はMoのシリサイド化膜3の場合について説明した
が、WあるいはTaのシリサイド化膜3の場合であって
もよく、同様の効果が得られる。
Although the case of the Mo silicide film 3 has been described above, the case of the W or Ta silicide film 3 may also be used, and similar effects can be obtained.

その他、これらこの発明のシリサイド化膜3はガラス基
板1との接着性も従来の場合に比べ榴めてよい。
In addition, the silicided film 3 of the present invention has better adhesion to the glass substrate 1 than in the conventional case.

なお、上記第2図の実施例では、ガラス基板1上KMo
、WあるいはTaのシリサイド化膜3を直接被着した場
合について説明したが、第3図に示すように、石英等の
ガラス基板1上にポリシリコン膜4を100OAの膜厚
に被着した後、このポリシリコン膜4上K、Moまたは
WあるいはTaのシリサイド化膜3を200 A程度の
膜厚に被層した2層の間接被着構造にしてもよく、この
場合にはシリサイド化膜3の接着力を強化できるばかり
でなく、当然使用される硅化金属の節減にもなる。
In the embodiment shown in FIG. 2 above, KMo on the glass substrate 1 is
, W or Ta silicided film 3 is directly deposited, but as shown in FIG. A two-layer indirect adhesion structure may be used in which a silicided film 3 of K, Mo, W, or Ta is coated on the polysilicon film 4 to a thickness of about 200 A. In this case, the silicided film 3 Not only can the adhesive strength of the adhesive be strengthened, but also the amount of metal silicide used can be reduced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、ガラス基板 。 As explained above, the present invention uses a glass substrate.

上にMoまたはWあるいはTa等のシリサイド化膜を形
成し、これをパターン形成マスクとして使用するように
しているので、エツチング速度が従来のCrの金属薄膜
に比べ極めて早く、しかも、微細パターンが容易に得ら
れ、かつ、ガラス基板に対する接着強度も大きいので、
信頼性の高いものが得られるという利点がある。
Since a silicide film of Mo, W, Ta, etc. is formed on top and used as a pattern forming mask, the etching speed is extremely fast compared to conventional Cr metal thin films, and fine patterns can be easily formed. and has high adhesive strength to glass substrates,
This has the advantage of providing highly reliable products.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は金属薄膜を使用した従来の半導体装置用パター
ン形成マスクの被着状態を示す断面図、第2図はシリサ
イド化膜を使用したこの発明の半導体装置用パターン形
成マスクの被着状態を示す断面図、第3図はポリシリコ
ン膜を介しその上にシリサイド化膜を被着させたこの発
明の他の実施例を示す断面図である。 図中、1はガラス基板、2は金属薄膜;3はシリサイド
化膜、4はポリシリコン膜である。 なお、図中の同一符号は同一または相当部分を示す。 代理人 大岩増雄 (外2名) 第1図 第2図 第3図
FIG. 1 is a sectional view showing the state of application of a conventional pattern forming mask for semiconductor devices using a metal thin film, and FIG. 2 shows the state of application of the pattern forming mask for semiconductor devices of the present invention using a silicided film. FIG. 3 is a cross-sectional view showing another embodiment of the present invention in which a silicide film is deposited on a polysilicon film through a polysilicon film. In the figure, 1 is a glass substrate, 2 is a metal thin film, 3 is a silicided film, and 4 is a polysilicon film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3

Claims (5)

【特許請求の範囲】[Claims] (1) ガラス基板上に被層されたマスクを、モリブデ
ンまたはタンタルあるいはタングステンのシリサイド化
膜から構成したことを特徴とする半導体装置用パターン
形成マスク。
(1) A pattern forming mask for a semiconductor device, characterized in that the mask layered on a glass substrate is composed of a silicided film of molybdenum, tantalum, or tungsten.
(2) ガラス基板は、石英ガラスで構成したことを特
徴とする特許請求の範囲第(1)項記載の半導体装置用
パターン形成マスク。
(2) The pattern forming mask for a semiconductor device according to claim (1), wherein the glass substrate is made of quartz glass.
(3) シリサイド化膜は、膜厚を500Aないし10
00Aの厚さに設定したことを特徴とする特#!F請求
の範囲第(11項記載の半導体装置用パターン形成マス
ク。
(3) The thickness of the silicide film should be between 500A and 10A.
Special feature: 00A thickness! F Claim No. (11) A pattern forming mask for a semiconductor device according to claim 11.
(4) シリサイド化膜は、ガラス基板上尾1000A
8度の厚さに仮着したポリシリコン膜を介してその上1
c20OA程度の厚さに形成させたことを特徴とする特
許請求の範囲第(1)項記載の半導体We#It用パタ
ーン形成マスク。
(4) The silicidation film is 1000A above the glass substrate.
1 on top of it through a polysilicon film temporarily attached to a thickness of 8
The pattern forming mask for semiconductor We#It according to claim (1), characterized in that it is formed to a thickness of approximately c20OA.
(5) シリサイド化膜は、ICB法で形成したことを
特徴とする特許請求の範囲第f11項、第(3)項ある
いは第(4)項のいずれかに記載の半導体装置用パター
ン形成マスク。
(5) A pattern forming mask for a semiconductor device according to any one of claim f11, claim (3), and claim (4), wherein the silicided film is formed by an ICB method.
JP59061372A 1984-03-27 1984-03-27 Mask for forming pattern for semiconductor device Granted JPS60202441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59061372A JPS60202441A (en) 1984-03-27 1984-03-27 Mask for forming pattern for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59061372A JPS60202441A (en) 1984-03-27 1984-03-27 Mask for forming pattern for semiconductor device

Publications (2)

Publication Number Publication Date
JPS60202441A true JPS60202441A (en) 1985-10-12
JPH0366656B2 JPH0366656B2 (en) 1991-10-18

Family

ID=13169271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59061372A Granted JPS60202441A (en) 1984-03-27 1984-03-27 Mask for forming pattern for semiconductor device

Country Status (1)

Country Link
JP (1) JPS60202441A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62153957A (en) * 1985-12-27 1987-07-08 Hoya Corp Photomask blank and photomask
JPS62229152A (en) * 1986-03-31 1987-10-07 Arubatsuku Seimaku Kk Photomask and its production
JPS62234163A (en) * 1986-04-04 1987-10-14 Arubatsuku Seimaku Kk Photomask and its production

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157247A (en) * 1981-03-23 1982-09-28 Nec Corp Optical exposure mask

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157247A (en) * 1981-03-23 1982-09-28 Nec Corp Optical exposure mask

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62153957A (en) * 1985-12-27 1987-07-08 Hoya Corp Photomask blank and photomask
JPH0473940B2 (en) * 1985-12-27 1992-11-25
JPS62229152A (en) * 1986-03-31 1987-10-07 Arubatsuku Seimaku Kk Photomask and its production
JPS62234163A (en) * 1986-04-04 1987-10-14 Arubatsuku Seimaku Kk Photomask and its production

Also Published As

Publication number Publication date
JPH0366656B2 (en) 1991-10-18

Similar Documents

Publication Publication Date Title
US4722878A (en) Photomask material
US4873163A (en) Photomask material
US4876164A (en) Process for manufacturing a photomask
JPS59153A (en) Formation of resist mask having resistance to plasma etching
JPH0435743B2 (en)
JPH0434144B2 (en)
JPH11231161A (en) Process for manufacturing plane optical wavegude within single chamber
US4792461A (en) Method of forming a photomask material
JPS63214755A (en) Photomask
JPH0466345B2 (en)
JPS60202441A (en) Mask for forming pattern for semiconductor device
JPH03116147A (en) Photomask blank
JP2909317B2 (en) Photo mask
JPH061367B2 (en) Photo mask
JPS5931975B2 (en) How to make an inversion mask
JPH061366B2 (en) Photo mask material
JPH0284723A (en) Dry etching
JPS6278557A (en) Photomask
JPS6410062B2 (en)
JPS6212502B2 (en)
JPS604271B2 (en) Dry etching method for chromium-based metal film
JPS60192947A (en) Photomask material for fabricating semiconductor device
JPH0667404A (en) Production of photomask
JPS63157154A (en) Formation of mask pattern
JPH0690508B2 (en) Photo mask

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term