JPS58158931A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the outward diffusion from the PSG film to the P type layer of the titled semiconductor device when the corner part of an window is formed into a gentle shape by performing a heat treatment by a method wherein the aperture section of the PSG film on an Si substrate, including P type impurities, is covered by an SiO2 thin film. CONSTITUTION:A P-channel transistor is formed on an N type Si substrate by performing the method heretofore in use. After the aperture section has been covered by the PSG film 5 and a connection window has been provided, thin thermal oxide films 8 and 9 are formed at a low temperature. A CVD film containing no impurities may be used instead of said thermal oxide films 8 and 9. Subsequently, the corners of the PSG aperture section are made round by performing a heat treatment. At this time, the P-diffusion from the PSG to P<+> source and drain 1 and 2 is blocked by the thermal oxide films 8 and 9, thereby enabling to improve the yield rate and the reliability of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an integrated circuit including a P-channel transistor.

Integrated circuits containing N-channel transistors use Linderash technology, which has greatly improved yield and reliability. This is because when a contact hole is just opened, a sharp corner is formed in the contact hole of the phosphor glass film of the surface insulating film, so if Alt is deposited on this surface and patterned to conduct wiring, A. ! A break in the wiring has occurred! In order to avoid this, high-temperature heat treatment is applied to make the corners mottled to prevent wire breakage. This method is called lindarashi, however, this lindarashi t-P+
When heat treatment is performed on an integrated circuit including a Jannel transistor, phosphorus jumps out of the phosphor glass film during heat treatment, a9t faces into the source and drain regions of the P-channel transistor through the contact hole, and is deposited on the surface of the L region. An N-type layer is formed and a PN junction occurs. For this reason, Alt-
Even if source and drain electrodes are formed by vapor deposition, there is a PN! between these electrodes and the source and drain regions! Unless the a-coupling is present, ohmic contact becomes impossible. FIG. 1 is a diagram explaining this, and 10 is an N-type silicon semiconductor substrate;
1.2 is a P+ type diffusion layer 13 that becomes the source and drain regions
4 is a field and gate insulating film, 4 is a polycrystalline silicon film serving as a gate electrode, and 5 is a phosphorus glass film deposited by chemical vapor deposition (CVD) or the like. 6.7 is an N+ diffusion layer formed near the exposed surface of the source/drain region 1.2 where phosphorus jumps out from the phosphorus glass film 5 during the softening treatment of the phosphorus glass film and enters the source/drain region 1.2.

In an N-channel transistor, this N diffusion layer has the same conductivity type as the source, doe, and L regions, so there is no problem, but in a P-channel transistor, a PN junction is formed in the source and drain regions, and the AI electrode and the source and drain regions are connected to each other. This causes contact failure and becomes a big problem.

The present invention has been made in an attempt to improve this problem, and forms a thin non-doped CVD film or a thin thermal oxide film on the exposed surface portions of the source and drain regions to prevent the formation of N2 diffusion.

This will now be explained in detail with reference to examples.

FIG. 2 shows an embodiment of the present invention, in which 10 is an N-type silicon semiconductor substrate, 1.2 is a P'fIl diffusion region that forms the entire source and drain region, 3 is a field and gate insulating film, and 4 is a polygonal silicon semiconductor substrate. The crystalline silicon gate electrode 5 is a phosphor glass film. The method for forming these regions and films is the conventional one, and then a hole is made in the phosphorus glass film deposited on the surface, and a thin non-doped CVD film is deposited on the exposed surface of the source and drain regions 1 and 2 using chemical vapor. Phase growth (CVD)
Alternatively, a thin thermal oxide film is formed by a low temperature oxidation method to provide 8.9. In this way, the non-doped CVD film 2 is constructed such that the thermal oxide films 8 and 9 act as a barrier against phosphorus out-diffusion, and the phosphorus in the phosphorus glass film diffuses from the contact hole into the source and drain regions 1 and 2. can be prevented.

The non-doped CVD film and thermal oxide film 8.9 generated here are removed by etching with a hydrofluoric acid solution before the next electrode wiring evaporation, so that they will not interfere with the contact. According to the present invention, the exposed surfaces of the source and drain regions of a semiconductor device such as a P-channel transistor are covered with a thin oxide film, thereby reducing out-of-contamination of phosphorus from the phosphorus glass film that occurs during rinsing. It is possible to prevent fading and improve the manufacturing yield and reliability of semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a P-channel transistor at the stage of Rindralash, ji! FIG. 2 is a sectional view illustrating the present invention in detail. In the same figure, 182...P type source, drain region, 30
．． . ...Insulating film, 4...Gate electrode, 5...
・11 N glass film, 6, 7...N diffusion layer, 8
．． 9...Non-doped CVD film or thermal oxide film, 1
0...Silicon semiconductor substrate.

Claims (2)

[Claims] (1) A phosphorus glass film deposited on a silicon semiconductor substrate having a P-type impurity region is opened to reach the impurity region, and then heat-treated to create steep angles in the openings and other parts of the phosphorus glass film. In the method for manufacturing a semiconductor device, which includes a step of smoothing the surface of the impurity region, an oxide film layer that prevents phosphorus from out-developing from the phosphorus glass film to the P-type impurity region during the heat treatment is applied to the exposed surface of the impurity region. A method for manufacturing a semiconductor device. (2) Claim (1) characterized in that a non-doped CVDM1'k layer is formed by chemical vapor deposition or a thermal oxide film layer is formed on the exposed surface of the iP-type impurity region by low-temperature oxidation, and then heat treatment is performed. A method of manufacturing the semiconductor device described above.