JPS5886760A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration of a semiconductor device by forming the same conductive type layers as diffused layers adjacent to the respective diffused layer in a C-MOSFET device, thereby preventing the electrode window from being displaced out of the diffused layers. CONSTITUTION:A P type well 102 is formed on an N type Si substrate 101 by a conventional method, P type and N type source and drains 106, 107 are formed, an interlayer insulating film 8 is superposed, and a window 109 is selectively opened. Polysilicon 110 is covered, a PSG mask 111 is selectively formed, a P type layer 112 is formed by diffusion of B and then an N type layer 113 is formed by heat treatment. The mask 111 is then removed, and an Al electrode 114 is attached. According to this configuration, since the margin can be remarkably reduced upon improvement of the integration due to the presence of the layers 112, 113, even if an electrode window is displaced out of the source and drain layers, a P-N junction is not broken down, and the leakage current of the window can be prevented from increasing, thereby obtaining a semiconductor device having high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor integrated circuit device.

Complementary insulated gate field effect transistor (CM
O8 transistor) has characteristics such as low power consumption, high speed operation, and high noise margin, so
CMO8) Semiconductor integrated circuits using transistors have been attracting attention in recent years. Furthermore, as the degree of integration increases, the margin for alignment in photoetching has decreased significantly, resulting in inconveniences such as the so-called "external contact" in which the companion opening for connection with the metal wiring protrudes outside the diffusion region. As a countermeasure to this problem, a method is usually used in which an opening is formed in the insulating film and then impurities of the same conductivity type are introduced into each impurity region. However, in CMO8) transistors, there are two types: N type and P type.
Because there are different types of impurity regions, when placing the impurity region in the opening, a mask must be used to create the opening over the impurity region of the opposite conductivity type to the impurity to be introduced, and two photolithography steps are required. , there were problems such as an increase in the manufacturing process.

An object of the present invention is to provide a complete method for manufacturing a semiconductor device using a %CMO8)9 transistor, which significantly improves the degree of integration.

The present invention provides a method for manufacturing a semiconductor device using a complementary insulated gate field effect transistor, in which an impurity well of an opposite conductivity type is further provided in an impurity well of an opposite conductivity type selectively provided in a semiconductor substrate of a -conductivity type. The first and Second
After forming an opening in an insulating film on the source/drain/impurity region of the semiconductor substrate, growing polycrystalline silicon on the semiconductor substrate,
Further, an oxide film containing impurities of one conductivity type (or opposite conductivity type) is selected for the opening of the insulating film formed on the first source/drain impurity region (or second source/drain impurity region). After growing the opposite conductivity type (or -
conductivity type) impurity is implanted into the second source.
An impurity region of the opposite conductivity type (or - conductivity type) is formed in the opening of the insulating film formed on the drain impurity region (or the first source/drain impurity region), and then by heat treatment, the - From the oxide film containing impurities of conductivity type (or opposite conductivity type), through the polycrystalline silicon, the first
After diffusing an impurity of one conductivity type (or opposite conductivity type) into the opening of the insulating film formed on the source/drain impurity region (or the second source/drain impurity region), type (or opposite conductivity type) impurity? Contains oxidized ffl? The first and second source/drain impurity regions and the metal wiring are connected through the opening in the insulating film.

According to the present invention, in a semiconductor integrated circuit using a CMO8 transistor tube, the inconvenience of external contacts can be solved with a slight increase in the number of manufacturing steps, and the degree of integration can be significantly improved.

Next, an embodiment of the present invention will be described with reference to the drawings. This embodiment relates to an integrated circuit device using CIV108) transistors and a method for manufacturing the same.

1 to 5 show cross-sectional views of embodiments of the present invention.

Boron is added to the N-type silicon substrate 101.

Cl2O is diffused for a time to selectively form a P well 102. Next, in the inactive region, there is a field oxide film 10 with a thickness of 1 μm.
A Cu 11-oxide film 104 of 1000 μm is grown in the active region. Crystalline silicon with N-type impurities diffused thereon is grown, and a gate electrode 105 is formed by photolithography.

Next, N type silicon substrate 101 KP type impurity diffusion layer 10
6, 107 N-type impurity diffusion layers are formed in the P well, each having a junction depth of 0.5 μm.

Coconut 2nd layer insulation M toslfr by CVD method
0, s μm, and an opening 109 is formed by photolithography.

Figure 3: Polycrystalline silicon film 110'ft0.2
A phosphorus glass (PEG) film Bt was grown to a thickness of 0.5 μm, and a P channel ~
The phosphorus glass film 1111 on the 10S transistor region is removed, and boron ions are implanted using the phosphorus glass film Ill as a mask for the N channel MOS transistor region to form a %P type impurity diffusion layer 112.

Second, heat treatment is performed at 1000''C for 10 minutes to diffuse phosphorus into the e°P well 102 included in the phosphorus glass film 111, forming an N-type impurity diffusion layer 113.

Figure 5: Next, the phosphor glass film 111e is removed and 1,0
The aluminum wiring electrode 114 is formed by depositing the aluminum using a chemical beam evaporation method of μn1.

Even when the CMO 8) obtained in this way becomes an external contact, the contact point is removed from the opening 109.
Channel MO8) A P-type impurity is introduced into the transistor side, and a P-type impurity diffusion layer 112 is formed.
qO8) transistor side N4 (1! Impurity is introduced,
Since the N-type impurity diffusion layer 113 is formed, the PN junction between the impurity diffusion l- and the substrate is not destroyed by the external contact. In addition, since the polycrystalline silicon film 110 is located in the opening 109, the opening 109 does not become large even during the process of removing the phosphor glass film 1111 twice, and the PN junction due to the impurity diffusion layer introduced through the opening 109 is The total effect of preventing damage cannot be reduced. Therefore, an increase in leakage current in the opening for connecting the impurity diffusion layer and the aluminum wiring can be prevented, and a highly reliable integrated circuit device can be obtained.

[Brief explanation of the drawing]

FIGS. 1 to 5 1/-i are sectional views showing the steps of an embodiment of the present invention. In the figure, 101...N-type silicon substrate, 102...P well, 103...
・Field oxide film, 104...Gate oxide film, 105...Gate '1i! pole, 10
6...P-type impurity diffusion layer, 107...
・N-type impurity diffusion layer, 108... interlayer insulating film, 109... opening, 110... polycrystalline silicon film, 111... phosphorous glass film,
112...P-type impurity diffusion layer, 113...
. . . N-type impurity diffusion 71.114 . . . Aluminum wiring is used as a pole. Ward

Claims (1)

[Claims] In a method for manufacturing a semiconductor device using a complementary insulated gate field effect transistor tube, a first impurity well of one conductivity type further provided in an opposite conductivity type impurity well selectively provided in a -conductivity type semiconductor substrate; 1 said first and second sources connecting metal wiring to each of said source/drain impurity region and a second source/drain impurity region of opposite conductivity type selectively provided on said semiconductor substrate; - After forming an opening in the insulating film on the drain impurity region, growing polycrystalline silicon on the semiconductor substrate, and then growing polycrystalline silicon on the first source-drain impurity region (or Tsumugi second source-drain impurity region). After selectively growing an oxide film tube containing impurities of one conductivity type (or opposite conductivity type) in the opening of the insulating film formed in
of the opposite conductivity type (or -conductivity type) is implanted into the opening of the insulating film formed on the second source/drain impurity region (or the first source/drain impurity region). An impurity region is formed, and then heat treatment is performed to form the fourth source/drain impurity region (or the second source/drain impurity region) through the polycrystalline silicon from the oxide film containing impurities of the − conductivity type (or opposite conductivity type). - A method for manufacturing a semiconductor device, characterized in that an impurity of one conductivity type (or reverse conductivity t' type) is diffused into the opening of the insulating film which is left open on the drain impurity region.