JPS58148930U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58148930U
JPS58148930U JP4714882U JP4714882U JPS58148930U JP S58148930 U JPS58148930 U JP S58148930U JP 4714882 U JP4714882 U JP 4714882U JP 4714882 U JP4714882 U JP 4714882U JP S58148930 U JPS58148930 U JP S58148930U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
semiconductor equipment
mesa groove
semiconductor
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4714882U
Other languages
English (en)
Inventor
戸嶋　正征
筧　二朗
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP4714882U priority Critical patent/JPS58148930U/ja
Publication of JPS58148930U publication Critical patent/JPS58148930U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は両メサ形半導体ペレットの一例を示す断面図、
第２図乃至第５図は第１図の半導体ペレットのマウント
工程を説明するための各動作時の　　　７断面図、第６
図及び第７図は本考案による半導体　　　−ペレットの
一実施例を示す断面図及び裏面図、第８図は第６図の半
導体ペレットのマウント時での部分拡大断面図である。 １′・・・・・・半導体ペレット、３・・・・・・メサ
溝、５・・・・・・絶縁保護膜、１０・・・・・・基板
、１１・・・・・・半田、１４・・・・・・金属被膜。

Claims (1)

    【実用新案登録請求の範囲】
  1. 裏面周辺部に形成し、たメサ溝に絶縁保護膜を被着形成
    した半導体ペレットを半田を介して基板上にマウントし
    た半導体装置において、前記半導体ペレットのメサ溝の
    絶縁保護膜上に半田に対して濡れ性の良好な金属被膜を
    形成したことを特徴とする半導体装置。
JP4714882U 1982-03-31 1982-03-31 半導体装置 Pending JPS58148930U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4714882U JPS58148930U (ja) 1982-03-31 1982-03-31 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4714882U JPS58148930U (ja) 1982-03-31 1982-03-31 半導体装置

Publications (1)

Publication Number Publication Date
JPS58148930U true JPS58148930U (ja) 1983-10-06

Family

ID=30058118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4714882U Pending JPS58148930U (ja) 1982-03-31 1982-03-31 半導体装置

Country Status (1)

Country Link
JP (1) JPS58148930U (ja)

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