JPS58146376A - Pinball machine - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention The present invention secures the right to win by a pachinko ball flying into a predetermined winning hole, and by having a pachinko ball flying into a winning hole different from the predetermined winning hole. This is about a pachinko machine that allows you to exercise your right to enter.

In pachinko machines, one of the reasons for the increase in the number of players playing games is that players sweat during the game depending on the skill of the player.

+: Simplified from the perspective of Maruaki, the configuration of the present invention increases the winning rate to 6 when a pachinko ball hits the winning opening of the θr lid. One way to secure advantage is to set the solenoid in the driving state and secure the right to increase the winning probability, and the pachinko ball lands in a winning opening different from the prescribed winning opening, and, This pachinko machine has a right exercise circuit which is turned on when the previous winning bet securing circuit is in an on state and drives the solenoid fF9r for a fixed period of time to exercise the right secured by the previous winning bet.

Embodiments of the F+ invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 is a pachinko machine according to the present invention that can be placed on the table of 4. At the top of this accessory 1, - is a large prize opening 2, a special prize opening 2, and a melo 3, 4. is provided, and side wall prize openings 5 and 6 are provided on the 1st wall of both the immortals of the accessory 1. This accessory 1 has 7 eyes, and a plate 8 with 45 eyes is provided at the bottom. In this distribution, the 8th one is pushing forward from the unloading force, and each person Ji: 1
．． 12.5.4.5゜Distribution from 6 [Pachinko #9゜10 that flew into 17, this distribution protrudes from similar 8 and 7
Its course is changed by the arrow part 11, and the second line rolls forward of the plate 8. Sort & 8
Seven partitions 112.13 are provided at the front of the screen, and between these partitions and 12.12 there is a right securer p"i 14, and this right secured prize opening 14 has a shape shown in Fig. 2. A rights securing switch 15 is provided.
Regarding the function of the 1 securing switch 15, the function of the right securing switch 15 is -i/1. There is.

An attacker person σ゛ mouth 18 and 19 is provided below the accessory 1, and the IWl between this Aitzker person . This attacker 20 is the third
As shown in the figure, the opening/closing side (goods) is controlled by the solenoid 21.
In this sheep figure 6, 221
j Attacker City 11 (l14 Ruba one means invitation. At the top of the attacker person's drum [" 1B, 19, the Yu 1st" exercise prize opening 25.24 is respectively this attacker's prize [118
, 19. This right 1st exercise prize opening 25.24V Kohashin A.1' Bamboo switch 25.2
6 are set respectively.

As shown in Figure 1, the control switch 15 is connected to the Schmitt waveform shaping IP circuit 27, and the control switches 25 and 26 are connected to the Schmitt waveform shaping IP circuit 27.
Connect to q+mzs. Seamit Sakagata Nogata 1o
When the J path 27.28i and each switch 15.25°26 are closed, each outputs a high signal. The output signal of the Schmitt 2Ji shaped shaping circuit 27 has been input to the T flip-flop 29, and the Schmidt 2Ji shaped shaping circuit 28
The output signal is input to an AND circuit 60. T7
When the 1J block flop 11 is set and the switch is in the high state, when the f signal is input from the seamitz sakagata zangata kaigen 27, it becomes the low state. T flip Flora 1 time % 29 (f) Output signal is ant time g4t 6 [J and 4 hit binary -
It is input to the counter circuit 51. The 4-bit binary counter circuit 61 is reset and outputs a low signal to the r NAND circuit 32 when the 'r flip-flop circuit 29 is in a high state.

63 is a clock circuit, 34 is a power reset circuit, '#I11. The clock circuit 36
= 5 +y: tf The power reset circuit 34 outputs the reset signal purple OR circuit 35 and OR circuit 66. The OR circuit 35 is configured to output a reset signal outputted from the power reset circuit 64 or inputted from the NAND circuit 62 via the Seratoi G and the NOT circuit 67 to the flip-flop 1 circuit 29. The T flip clock 1 circuit 29 is reset to a low state when at least one of the power reset circuit 64 and the not circuit 37 is in a high state.

Clock signal A of clock circuit 58 is input to 4-bit binary-counter circuit 38. The 4-bit binary counter circuit has four output arms, and the output lines ■ and ■ are connected to the AND circuit 39, and the output line ■ is connected to the pilot lambtolife circuit 40, and the output Line ■ is 4-bit binary counter circuit 4
Connected to 1. For each output '/fM■ or ■,
A rectangular signal shown in FIG. 6 is flowing. Reference numeral 42 denotes a pilot lamp, which is in a blinking state when the power is turned on and the high lot lamp driver circuit 40 is intermittently turned on and off by the output signal from the 4-bit binary counter circuit 38.

Rights securing switch 15 and Schmitt waveform shaping circuit 27
The T-flip flow circuit 29 is a solenoid 21 that is turned on when a pachinko ball flies into a fixed winning opening to increase the probability of winning, and is set to a state of 1.
It roughly constitutes the right 1a protection circuit that secures the Rakshasa that increases the winning probability, and the Yuori exercise switch 25.26
and AND1 Kawaji 30 is when a person different from 19 "T's input*r" plays 5IQ, and (tl- profit securing circuit is on) 7, which constitutes a part of a right exercise circuit that turns on and drives the solenoid 21 for a predetermined period to exercise the secured right.

AND circuit j 1301d, T frill rough flo9f circuit 29 is in high state, and right dip switch 25.26
When at least one of the circuits is closed, the circuit No. 6 is output to the flip-flop 11 path 43, and the flip-flop circuit 43 is in the high state. The output signal of is knot 1
The 1 and NOT circuits 44, which have been input to the wi path 44 and the y-divider circuit 45, are the 4-bit binary counter circuit 4.
When the flip-flop circuit 43 is in the low state, the 4-bit binary counter circuit 41 is reset by the high signal output from the NOT circuit 44, and the 4-bit binary counter circuit 41 is reset. - If the counter circuit 41 is configured to output a low signal and the flip-flop circuit 46 is in a high state, this reset is canceled and the clock No. 11 shown in FIG. 7 is output. There is. A differential signal is output to the differential circuit 45 based on the difference in NL when the flip-flop circuit 43 changes from low to high, and this differential signal is input to the 4-bit binary counter circuit 38. The 4-bit binary counter circuit 58 can be reset by this differential No. 18. The relationship between the clock signal outputted from the 4-bit binary counter circuit 38 and the clock signal A outputted from the clock circuit 66 by -4t is explained based on FIGS. 5 and 6. A clock signal with a period twice as long as 16 is output from the output line ■, a clock signal with a period four times as long as 16 double no he J
The 4-bit binary counter circuit 68 receives 11 cents from the tarot signal if, I', f't every time it hits 11 cents. The I17 + I number is ■ [Save the power by 1 kund and repeat the clock signal shown in 6th and 1] j
Strengthen.

Describing the relationship between the 4-bit binary counter circuit 41 and the clock signals output from the 4-bit binary counter circuit 68 as follows, the 4-bit binary counter circuit 41 has three output lines ■'*C;)'+Q'
9, and outputs from the output shaft υ′.
)' The clock signal output from the output line ■ has a clock signal output from the output line ■ and the clock signal output from the output line ■'. It has a periphery 1 that is 16 times the clock signal output from the clock signal. Each output line ■′.

■/ , (The clock signal output from jr/ is input to AND-1 circuit 46. AND circuit 46f,
When each output line ■', (su', ■' is high), the reset signal 13 shown in FIG. The flip-flops 1 and 147 are activated by the clock signal output from the 4-bit binary counter circuit 41, and the reset signal B is input manually. shily '+ te (7) lt, I
l, maintain the high state, and this flop “flop 1t”
Output No. h of path 1 47 is solenoid dry circuit 48
and 4 bi soto binary counter circuit 31 and 4 pinodopa f nary counter lr! Enter lH%49 and 1. This 4-bit binary counter times and 14
Reference numeral 9 is set when the flip 7° tube circuit 47 is at high level, and outputs the clock signal input from the AND circuit 39 to the resistor-combination circuit 50. Resistor dollar waveform sum h'2.1111 path 5° output by waveform No. 44 is variable oscillation time % for voltage.
51 K input This is input to the audio amplification I'1TIl path 52, and is converted into sound from the speaker 53. 54 is an AND circuit, and this AND circuit 5
4 is inputted with the output signal of the T-flip 70 tube circuit 29, the output signal of Taro 9248 from the output line 1 of the 4-bit binary counter circuit 68, and the output signal from the NAND circuit 32. 29 and the NAND circuit 32 are high, the clock signal from the output line (2) of the 4-hit binary counter circuit is outputted to the pilot lamp drive circuit 55, and the pilot lamp 56V'i is connected to this IIA driving circuit. 55, the light turns on and off repeatedly.

Next, the effect will be explained.

(b) Turn on the power.

When the power is turned on, a reset signal is output to the OR circuit 35 and the OR circuit 36, and this reset signal is output to the T flip-flop circuit 29, the flip-flop circuit 46,
The signal is input to the flip-flop circuit 47. Then, T
Flip-flop circuit 29, flip-flop circuit 45
, the flip-flop circuit 47 becomes a low state. Since the flip-flop circuit 43 is in the low state, the NOT circuit 44
is in a bad state, the 4-bit binary counter circuit 41 is reset, and output of its clock signal is prohibited.

When the power is turned on, the clock circuit 33 outputs a clock signal A, and this clock signal A is input to the 4-bit binary counter circuit 38. Since the clock signal outputted from the output line (1) of the 4-bit binary counter circuit 68 is input to the pilot lamp drive circuit 40, the pilot lamp 42 blinks when the power is turned on.

Since the T-flip 70 knob 29 is in the low state regardless of whether the NAND circuit 32 is in the low state, the AND circuit 54 receives the clock signal output from the output line ■ of the -4-bit binary counter circuit 38. It does not output toward the pilot lamp 55. Therefore, the pilot lamp 56 is in an extinguished state.

The solenoid 21 is not activated because the flip-flop circuit 47 is in the low state, the attacker 20 is in the open state, and the 4-bit binary counter circuit 49 is not set because the flip-flop circuit 47 is in the low state. Therefore, no sound effect is generated from the speaker 53.

(b) During the game, the pachinko ball enters the winning hole of accessory 1, 2°5,
4.5.6 When a ball is hit by another person and the ball enters the right securing prize opening 14, and the right securing switch is momentarily closed.

When the rights securing switch 15 is closed, the output signal from the Schmitt waveform shaping circuit 27 changes the T flip-flop 29 from low to high. This signal is the AND circuit 6
0 and 4-bit binary counter circuit 61. Since the 4-bit binary counter circuit 31 is reset 14 when the T flip-flop 29 is high,
The output signals output from the two output lines of 7 are both low, and the NAND circuit 62 outputs a high signal. satisfies the high condition, the clock signal of the output line (3) of the 4-bit binary counter circuit 38 is output, and the pilot lamp 56 blinks, indicating that the right has been generated and secured. Ru. This state of securing rights will be extinguished under the following six conditions.

ψ When the right securing switch 15 is closed while the T flip-flop 29 is in the high state.

■ When the power is turned off.

■ If you exercise the right to tir the number of legs.

The termination of this right after a certain number of rights have been exercised will be discussed later.

()→ When the right is secured and a pachinko ball flies into either of the right winning slots 23 and 24.

The AND circuit 30 outputs a no-y signal 7, and the flip-flop N path 43 changes from low to no-y.

The differentiating circuit 45 calculates N1. when the flip-flop N path 43 changes from low to high. Since the differential A8- is output at the rising edge, the 4-hint binary counter circuit 38
1″r, -1 & reset, clock circuit 3
The clock signal A from 6 is counted again and the clock signal (N number) shown in FIG. 6 is output.

In the 4-bit binary counter circuit 41, since the NOT circuit 44 becomes low when the flip-flop N path 46 is A), the reset is completely released and the clock signal shown in FIG. 7 is output. Figure 7, 81s! As shown in the figure, the reset signal B output from the AND circuit 46 and the output line ■'
Compared to the clock signal output from the output line ■I, the rise of the clock 4g output from the output line ■I is earlier than that of the clock signal output from the output line ■'.
When the clock No. 215 from .

When the flip-flop 47 becomes NO, the solenoid drive circuit 48 is driven, the solenoid 21 is activated, and the attacker 20 is opened. with, 4
This NO/YES signal is input to the hit binary counter w661, and it is counted that the first exercise of the right has been exercised once.

Since the 4-hit binary counter circuit 49 is set when the flip-flop circuit 47 is high, it outputs the clock signal from the AND circuit 39 to the resistor dollar-saka type synthesis circuit 50 and operates the solenoid 21 as well. A sound effect will be generated.

The flip-flop lol path 47 is reset by the reset signal B output from the AND circuit 46, and the ninth
As shown in the figure, the signal changes from high to low after a predetermined period of time has elapsed.

As a result, the operation and assistance of the solenoid 21 is stopped, and the generation of sound effects is stopped, and the flip-flop circuit 43 is also reset by reset No. 48B.
The flip flop circuit 43 goes from high to low, the NOT circuit 44 goes high, and the 4-bit binary counter circuit 41 is reset.The output of the clock signal is then stopped, and the first clock signal is activated. ends. In this way, the exercise is repeated, and the number of times the right is exercised is counted by the 4-bit binary counter circuit 31vc. When the number of times reaches 10, the 4-bit binary counter circuit A state in which both high signals are output from the two output lines of 31 has been realized, and the NAND circuit 32
becomes low, so the NOT circuit 57 becomes high, and this is input to the T flip-flop 29 via the OR circuit 35, so the T flip knob 29 is reset and goes from high to low, and the right goes to 7P. Do 5.

As clarified above, the present invention is based on the rights created by
Since the player's desire to play (i-) can be increased, the player's desire to play can be increased.

It should be noted that the examples show one configuration example of the present invention, and may be modified as appropriate within the scope of the purpose of the present invention.
There are 4 degrees.

Congratulations on the 11fl car of the 4 drawings. Figure 1 is a schematic view of the pachinko machine according to the present invention (viewed from the entire front 1H0 direction). Figure 2 is a rights securing switch for a pachinko machine according to the present invention. Noga 1st celebration map.

FIG. 6 is a diagram showing the connection relationship between the attacker and the solenoid used in the pachinko machine according to the present invention.

Figure 8g4 is a block diagram of a circuit used in the pachinko machine according to the present invention.

FIG. 5 is a clock signal diagram of a clock circuit applied to the present invention.

6 and 7 are signal dk diagrams of clock signals output from the binary counter 1 channel 38 and 41, respectively.

18 are signal hourglass diagrams of the reset signal output from the AND circuit 46.

1-1.91%l is a drum-shaped diagram of the output number output from the 7 resobufloso 1 circuit 47.

14 °,, 4;71
5°°゛Gori securing switch 23.24...4E interest rate 1 history personnel mouth 25.2
6...Gon O I (Row 1 history switch 27.28...Schmidt-shaped shaping circuit 29...T flip-flop 30...AND circuit 46...flip-flop circuit 48...Solenoid drive circuit (1 other person) 1 Continuation of Figure 1, page 1 0 Inventors Sadayuki Takahashi 1-487-4 Aioi-cho, Kiryu City 0 Inventors Momoji Kanai 5-21 Orihime-cho, Kiryu City @ Inventor Reiji Fujita Kiryu Kuruma 6-8-6 @ Inventor 1241-5 Kuroyo, Hishicho, Ropponfutsu, Kiryu-shi Inventor Kiyoshi Otani 63-2 Daaza Kirihara, Omama-cho, Yamada-gun, Gunma Prefecture Inventor Hayashi Nibe Maebashi 711-3 Aramaki-cho, Ichi Procedural amendment (method) 1 Indication of case 1982 Patent Application No. 30257 2, Title of invention Pachinko machine 3, Person making the amendment Relationship with the case Patent applicant 5, Amendment order attached with H

Claims (1)

[Claims] (1) The solenoid that is turned on when a pachinko ball enters the "Gon No. 1" securing prize [] and increases the probability of winning is set to the "J (Itif state), and the winning probability is set to 1".
When a pachinko ball flies into a shield that is different from the right securing circuit that secures "the first right to increase the rate" and the winning opening for securing the use of the game, and the pachinko ball flies into the user 1' A pachinko machine comprising: a control circuit that is turned on when the securing circuit is in an on state to drive an Ail Apirenoid for a predetermined period of time to exercise the secured rights.