JPH0573431B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention is capable of converting the playing area of a game board into a first state in which the ball is not accepted by an electric drive source and a second state in which the ball is easily accepted. The present invention relates to a pachinko machine that is provided with a variable winning device having a movable member, first and second operating winning ports for activating the variable winning device, and further provided with a special winning hole in the variable winning device.

(Prior Art) In general, when a batted ball enters the operating prize opening, simply converting the movable member of the variable prize winning device to the second state where the batted ball is easily accepted will result in a monotonous game and will reduce the interest of the pachinko game. I can't get excited.

For this reason, a variable prize winning device is operated according to a plurality of prize states to diversify game contents.

For example, the activated winning holes are divided into two types: the first activated winning hole and the second activated winning hole, and if you win in the first activated winning hole, you will only win once, and if you win in the second activated winning hole, you will only win once. It is conventional practice to convert the movable member into the second state only twice.

(Problems to be Solved by the Invention) However, in conventional pachinko machines, it is difficult to determine whether a prize has been won in the first operating winning hole or the second operating winning hole.
The player could only recognize the number of times the movable member was opened and closed by visually checking the number of times the movable member was opened and closed.

For this reason, not only is the player required to be extra attentive to counting the number of times the movable member is opened and closed during the game, but the development of the game content is complicated and difficult to understand, and it lacks interest. It was becoming.

The present invention aims to solve this problem.

The present invention creates a normal game state that is not directly connected to the operation of the variable prize winning device and a special prize mode game state that enables the operation of the variable winning device, further increases the interest of pachinko games, and provides a first operating prize opening. Alternatively, the purpose is to notify the player visually and audibly which prize has been won in the second operating prize opening, and to enable the player to immediately and reliably determine changes in the status of the variable prize winning device. do.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a first state in which the ball is not accepted by an electric drive source and a second state in which the ball is easily accepted within the game area of the game board. A pachinko machine is provided with a variable winning device having a movable member that can be converted into a variable winning device, first and second operating winning ports for activating the variable winning device, and further provided with a special winning hole in the variable winning device. a sound generating device, a display means provided in the game area of the game board, and a control device for controlling the sound generating device, the display means, and the electrical drive source, the control device comprising: a first A first timer means for regulating the effective time during which the movable member enters the second state M times after the detection output of the first operating switch belonging to the operating winning opening, and a detection output of the second operating switch belonging to the second operating winning opening. a timer generating means comprising a second timer means for regulating an effective time during which the movable member is later placed in the second state N times; and upon receiving a signal from the timer generating means, an electric drive source, a display device, and an audio and timing control means for activating the generator, and when the first actuation switch is activated under normal gaming conditions, the timing control means causes the first output to change from the initial state for an effective time determined by the first timer means. state and activates the electric drive source, display device, and sound generation device, and when the second operating switch is activated under the normal gaming state, the operation is performed from the initial state for an effective time determined by the second timer means. Shifts to the second output state, operates the electric drive source, display device, and audio generator, and then enters the special winning slot within the valid time period during which the conversion operation of the second state is performed M times or N times. When a prize is won, the system shifts to the third output state for the special prize mode gaming state, and the movable member is continuously activated many times based on the timer signal corresponding to the special prize mode gaming state from the timer generating means. The configuration is such that the conversion operation is performed.

(Example) Hereinafter, the present invention will be explained based on an example of a pachinko machine shown in the drawings.

In FIG. 1, in the center of the game area 4 of the game board 1 divided by the guide rail 2 and the inner partition plate 3, there is a first state (FIG. 2) in which a game ball, that is, a hit ball is not accepted, and a hit ball. A variable prize winning device 10 is provided which has a movable piece 11 as a movable member that can be converted into a second state (FIG. 3) in which a prize can be easily accepted and a prize can be won.

Lamps (warning lamps) L2 and L3 imitating railroad crossing warning lights are disposed on both left and right sides of the game area 4 as display means for players to see.

Further, within this game area 4, general winning devices 5, 6, out holes 7, guide nails, etc. are provided.

The general winning devices 5, 5 located on the left and right sides of the variable winning device 10 are dive-type winning devices that have a winning opening on almost the same plane as the game board 1, and the protruding parts around the winning opening are It is formed of a colored translucent member and functions as an illumination lamp (board lamp) L1 in cooperation with a lamp provided inside the device.

Below the variable winning device 10, first operating winning holes 8, 8 and second operating winning holes 9 are arranged side by side, and a ball detector is attached to each operating winning opening 8, 8, 9. I've let it happen.

In this specification, the ball detectors belonging to the left and right first operating winning ports 8, 8 are referred to as the first operating detector (first operating switch) SW1, and the ball detectors belonging to the second operating winning port 9 in the center are referred to as the first operating detector (first operating switch) SW1. is distinguished as a second operation detector (second operation switch) SW2.

In FIGS. 2 to 6, SOL is an electromagnetic solenoid that is an electrical drive source for converting the movable piece 11 as a movable member of the variable prize winning device 10.

To convert the movable piece 11 from the first state to the second state, the lever 13 pivotally attached to the plunger 12 of the electromagnetic solenoid SOL is sucked upward against the return spring 16, and the movable piece 11 is moved through the crank 14. This is done by rotating the drive shaft 15 of 11.

The variable winning device 10 has a window 1 provided on the board 10A.
It has a recessed chamber 18 projecting rearward from the recessed chamber 7, and within the recessed chamber 18 is a shunt shelf branching member 19 imitating a locomotive.

When the movable piece 11 is completely converted to the second state as shown in FIG. 3, the movable piece 11 coincides with the diverter shelf 19B extending on both sides of the central branch part 19A of the diverter shelf branching member 19, and the winning ball is Movable piece 11 and diversion shelf 19B
and falls into the branch gutter 20 inside the concave chamber.

Then, it passes through the diversion gutter 20 to the back side of the game board 1 and is guided into the collection gutter 23.

However, if a prize is won during the conversion between the first state and the second state, the concave chamber 1 of the variable winning device 10
8 below, it falls into either of the three winning holes arranged side by side on the front of the board, namely the left and right normal winning holes 21 or the special winning hole 22 in the center, and passes through the opening made in the board of the variable winning device. It passes through to the back side of the game board 1 and is guided into the collection gutter 23 as before.

In this case, only the winning balls from the central special winning opening 22 are detected by the ball detector (special winning detection switch) SW.
3 and then dropped into the collection gutter 23. This center special winning opening 22 is the left and right regular winning opening 21.
In order to allow the player to clearly identify the player, a V-shaped notch 24A is provided in the lower front plate 24, which is a component of the winning hole 22.

The winning balls from the above-mentioned branch gutter 20 and winning holes 21, 22 merge in the collecting gutter 23, are collected at the ball outlet 23A of the collecting gutter 23, and are led to a ball processing device (not shown).

At that time, these winning balls are detected by a ball detector (count switch) SW4 attached to the ball outlet 23A of the collection gutter 23.

In FIGS. 2 and 6, top prize openings 25 are provided on the left and right sides of the board 10A of the variable winning device 10, and an upper front plate 26, which is a component of the top prize opening 25, has A right number display 27 consisting of a 7 segment LED digital display is installed.

Furthermore, on the upper surface 18A and lower surface 18B of the recessed chamber 18, light emitting elements LA, LB, and LC made of LEDs are arranged sequentially from the front side toward the rear side.

In the branching shelf branching member 19 imitating a locomotive in the concave chamber 18, there is a branching part 19A formed hollow.
There is a lamp (inside case lamp) L0 at the rear of the locomotive, and an LED lamp (headlamp) L4 is installed in the headlight section of the locomotive.

A colored translucent plate 28 is fitted into the branching part 19A, that is, the front part of the locomotive, and the front part of the locomotive is illuminated by the lamp L1 inside the case.
It's starting to shine brightly.

Next, referring to FIGS. 7 to 10, a control device for controlling various warning lamps as a sound generating device and a display device, an electric drive source as a drive source for movable members, etc. will be explained.

First, in FIG. 7, numeral 30 is a reference time generating section as a timer generating means, which includes a clock generating circuit 31 that generates a 20 Hz clock, and a clock generating circuit 31 that generates a desired timer signal S1 upon receiving the clock from the clock generating circuit. .about.S9.

This timer generating means 30 includes a first timer means for regulating the effective time during which the movable member 11 is in the second state M times after the detection output of the first operating switch SW1 belonging to the first operating winning hole 8; After the detection output of the second operating switch SW2 belonging to the second operating winning opening 9, the movable member 11 is configured with a second timer means that regulates the effective time in which the movable member 11 is in the second state N times.

The details will be explained below.

In FIG. 8, the timer time generation circuit 32 has a first frequency divider 321 for the input clock, and the first frequency divider has timer signals T1 (0.2 seconds) and T2.
(0.4 seconds).

Further, the timer time creation circuit 32 includes a second frequency divider 3
22, a logic circuit 323 connected thereto, a D flip-flop 324 that performs an inverting operation upon receiving a pulse with a period of 0.4 seconds from the logic circuit, and a third frequency divider 325 whose input is the output of the flip-flop.
and a logic circuit 326.

A pulse is generated in the logic circuit 323 when 0.75 seconds have passed after the start of time measurement, and the OR gate 32
7 to clear the second frequency divider 322.

The flip-flop 324 is a movable piece timer that generates 0.75 seconds required for the opening/closing operation of the movable piece 11, and the 0.75 seconds required to energize the solenoid SOL as an electrical drive source from its output terminal Q. timer signal (start signal) T3,
Create T5.

From the next logic circuit 326, this open/close signal T
3. In addition to T5, timer signals T4 (1.2 seconds) and T6
(2.25 seconds), T7 (3.0 seconds), T8 (8.25 seconds), T9
(18 seconds) is taken out.

7, 8 and 9, 33 is a switch input reception circuit, 34 is a count circuit belonging to the count switch SW4, 35 is a normal operation reception circuit, 36 is a right number display circuit, 4
0 is an operation stepwise circuit; 50 is an operation timing generation circuit as a timing control means for receiving a signal from a timer generation means and operating an electric drive source for driving a movable member, a display device, a sound generation device, etc.; 6
0 is the lamp to be controlled, LOL, output circuit to LED, 70 is audio output timing creation circuit, 80
is a sound generation circuit.

In the operation step circuit 40 of FIG. 7, 41 is the output D0, D1,
It is an encoder with a priority function that receives D2 and D3 as inputs, detects the most significant "1" of the inputs, and outputs the address as a 2-bit binary code.

The input reception circuit 33 in FIG. 8 includes a D flip-flop FF1 belonging to the first operating switch SW1, a D flip-flop FF2 belonging to the second operating switch SW2, and a D flip-flop FF3 belonging to the special winning detection switch SW3. FF1
The outputs of Q of FF2, Q of FF2, and FF3 become D3, D2, and D1 inputs of the encoder 41.

D0, which is the lowest input of this encoder 41
As will be described later, the normal operation acceptance circuit 35 (eighth
Figure) is output.

43 is an up counter with preset;
The data preset as the initial state is determined by the output of the encoder 41.

In this example, of the 4 preset input bits,
The lower two bits are fixed as "00" and the outputs Q1 and Q0 of the encoder 41 are loaded into the upper two bits.

44 is a demultiplexer, which uses the inverted data of the upper two bits of the up counter 43 as selection inputs B and A, and outputs it to four output terminals 0 to 3.
select one of them and set the corresponding output terminal to “0”.

The output of the output terminal 3 of the demultiplexer 44 is used as a switch acceptance control signal SWC that controls permission and prohibition of switch acceptance regarding the operating switches SW1, SW2 or the special winning detection switch SW3.

If the switch acceptance control signal SWC is “0”,
Allow operation switches SW1 and SW2 to be accepted,
If it is “1”, acceptance of special winning detection switch SW3 is permitted.

In the operation timing generation circuit 50 of FIG.
51 and 52 are dual four-channel multiplexers with strobe inputs.

Each multiplexer 51, 52 selects the lower two bits of data of the up counter 43 from the selection input A,
As B, one of channel inputs X0 to X3 or Y0 to Y3 is selected and transmitted to output Z or W.

The strobe signal is the selected output of the demultiplexer 44 and is applied to the input terminal ST1 or ST2 of each multiplexer 51, 52.

Here, the multiplexer 51 is used as a multiplexer for normal operation (normal multiplexer), and the multiplexer 52 is used as a multiplexer for special operation (special multiplexer).

Of the X0 to X3 input terminals of the normal multiplexer 51, X0 receives the timer signal T4 (1.2 seconds) from the reference time generation circuit 30, and Y0 of Y0 to Y3 receives the timer signal T7 (3.0 seconds). The remaining input terminals are set to "0".

On the other hand, X0 to X3 of the special multiplexer 52
Among the input terminals, X0 has a reference time generation circuit 30.
A timer signal T8 (8.25 seconds) is applied to X1, and a timer signal T9 (18 seconds) is applied to X1.

Furthermore, among Y0 to Y3, Y1 and Y2 are “1”
The remaining input terminals are set to "0".

The outputs Z and W of the normal multiplexer 51 and the output Z of the special multiplexer 52 are connected to the OR gate 4.
5 to the clock input terminal of the up counter 43.

Furthermore, 53 indicates Q0 and Q of the up counter 43.
BCD with 1, 3, 2 as code input ABCD
- It is a decimal decoder.

Next, the control operation will be explained.

Initial Setting When the power is turned on, an initial reset pulse S0 is generated from the initial reset section 46 of the operation step circuit 40, and the up counter 43 is cleared.

This initial reset pulse S0 is also sent to the OR gate 351 of the normal operation acceptance circuit 35 in FIG. 8, causing the OR gate 351 to generate "1".

“1” generated in this normal operation acceptance circuit 35
becomes the D1 input of the encoder 41 of the operation step circuit 40.

Since D1 is the highest input of the encoder 41 here, the outputs Q1 and Q0 of the encoder 41 are "00".

At this time, an output valid signal GS indicating that the encoder output is valid appears in the encoder 41, and an enable output E0 indicating that the encoder input is not input.
disappears.

The output valid signal GS is taken out as a reset signal RE, and is sent to the flip-flop 352 of the normal operation reception circuit 35 and the flip-flop 4 for preventing malfunction.
9 and set their output terminals Q to "0".

Further, the reset signal RE resets the output terminals Q of flip-flops FF1 and FF2 of the switch input reception circuit 33 to the "0" state, and sets the output terminal of the flip-flop FF3 to the "0" state.

Further, the signal GS is sent to the reference time generation circuit 30 as a reset signal RE1 through the OR gate 47, and resets the clock generation circuit 31 and the timer time generation circuit 32.

Note that the reset of the timer time generation circuit 32 is performed using the second and third frequency dividers 322 and 325 in FIG.
Clearing means resetting the flip-flop 324, and clearing the first frequency divider 321 does not mean resetting the flip-flop 324.

On the other hand, the output code “00” of the encoder 41 is input to the preset inputs P3 and P2 of the up counter 43.
is applied, and the up counter 43 is preset to "0000".

The timing of this preset is determined by encoder 4.
When the enable output E0 of 1 disappears and the GS output is generated, the pulse generated in the AND gate 42 is
Load input terminal LOAD of up counter 43
This is done by joining.

When the content of the up counter 43 is "0000", the selection inputs B and A of the demultiplexer 44 are "11", so the demultiplexer 44 selects the output terminal 3 and sets only the output terminal 3 to "0". Make it.

Three outputs of the demultiplexer 44 are used as a switch admission control signal SWC.

Since the output terminals 0 to 2 for other strobe signals are "1", the outputs of multiplexers 51 and 52 are both disconnected.

In addition, since the selection input DCBA of the BCD-decimal decoder 53 is "1100" which is larger than the decimal "9", the outputs Q0 to Q9 are all "0", and the movable piece 11 normally controls the variable prize winning device 10 when playing the game. Closed to the sphere.

(a) Blinking of the light emitting element When the demultiplexer 44 selects the output terminal 3, the output terminal 2 is "1".

The enable input terminal of the demultiplexer 61 in the output circuit 60 is connected to the output terminal 2 of the demultiplexer 44 via the inverter 48.
It is connected to the.

Therefore, demultiplexer 61 is enabled.

The demultiplexer 61 receives timer signals T1 and T2 from the timer time generation circuit 32 at its selection input terminals A and B, and the light emitting elements LA,
The LB and LC drive circuits 605, 606, and 607 are sequentially energized.

Therefore, the light emitting elements LA, LB, and LC provided on the upper and lower surfaces of the recessed chamber 18 blink in sequence, and their lighting states cycle.

(b) Switch acceptance control signal “0” obtained at the output terminal 3 of the operating switch acceptance permission is the line 4
43 to the switch input receiving circuit 3 of FIG.
3 and NOR gates 335 and 3, respectively.
Through 36,337, flip-flop FF
Give "1" to the D input terminals of FF1, FF2, and FF3.

That is, regarding the operating switches SW1 and SW2.
The reception operation of FF1 and FF2 is permitted, and the reception operation of FF3 regarding special prize switch SW3 is prohibited.

Under this condition, when a batted ball enters the operating winning holes 8 and 9, the solenoid SOL is activated as follows.
(FIG. 4) is activated, and the movable piece 11 changes from the first state (closed state) in FIG. 2, in which no game ball enters the prize, to the second state (open state) in FIG. 3, in which it easily accepts batted balls. converted.

Control of the normal gaming state (a) Winning a prize in the first operation winning hole When a ball hits the first operation winning hole 8, 8,
Based on the detection output from the first actuating switch SW1, the upper warning lamp L3 as a display device lights up for 0.75 seconds in the following manner, and then the movable piece 11 as a movable member opens for 0.75 seconds.

Further, at the same timing as the movable piece 11, the lower warning lamp L2, which also serves as a display device, lights up and a whistle sound is generated.

First, win the first prize in the first operation prize opening 8,8 and win the first prize.
When the operating switch SW1 is turned on, the D flip-flop FF1 is triggered via the waveform shaping circuit 331.

Since the D input of FF1 is set to "1" in response to the switch admission control signal SWC "0" from line 443, the output terminal Q of FF1 is set to the state of "1".

The Q output of FF1 becomes the highest input D3 of the encoder 41, the output code "11" of the encoder 41 is applied to the preset inputs P3 and P2 of the up counter 43, and the up counter 43 is preset with "1100". be done.

Once preset, the FF1 and the reference time generating circuit 30 are returned to the reset state by the reset signal RE.

The upper warning lamp blinks. When the up counter 43 is preset to “1100”, the BCD-decimal decoder 5
Since the code input ABCD of No. 3 becomes "0000", the output terminal Q0 of the decoder 53 becomes "1", and the output terminal Q0 of the decoder 53 becomes "1", and the output terminal Q0 of the decoder 53 becomes "1".
and opens AND gates 63 and 66.

For this reason, first timer signal T3 (0.75 seconds)
is added to the drive circuit 603 of the upper warning lamp L3 as a display device through the AND gate 66 and the diode D3, and the upper warning lamp L3
lights up for 0.75 seconds.

Flashing of the lower warning lamp, opening/closing operation, and whistle sound When the above-mentioned 0.75 seconds have elapsed, the opening/closing signal T5 (0.75 seconds) appears through the AND gate 63.

The opening/closing signal T5 is applied to the lower warning lamp L2 drive circuit 602 through the diode D1, and lights the lower warning lamp L2 for 0.75 seconds.

Further, the opening/closing signal T5 is applied to the drive circuit 604 of the solenoid SOL through the diode D5, and energizes the solenoid SOL for only 0.75 seconds to open/close the movable piece 11 as a movable member once.

Furthermore, the opening/closing signal T5 is sent to the sound generation circuit 80 through the AND gate 72 and the diode D5 of the sound output timing generation circuit 70, activates the whistle sound generation circuit 81, and outputs a "port" signal from the speaker through the mixing circuit 84 and amplifier 85. ” will be emitted once.

Validity period “Validity period” is special prize detection switch SW
This is the period during which reception of items 3 is permitted.

Selection input B of multiplexers 51 and 52,
Since A remains at "00" which was before the operating switch SW1 was turned on, the normal multiplexer 51 selects the channel X0.

On the other hand, the selection inputs B and A of the demultiplexer 44 change from "11" to "00" by the preset of the up counter 43, and only the 0 becomes "0", and the strobe signal is sent to the normal multiplexer 51. It is given to terminal ST1.

Therefore, the normal multiplexer 51 receives the open/close signal T4 (1.2 seconds) from the timer time creation circuit 32 at the input terminal of the channel X0.
It enters the "validity period" state in which it expects to be sent.

Also, during this time, 3 of the demultiplexer 44
Output (switch reception control signal SWC) is “1”
Therefore, the D input terminal of the D flip-flop FF3 is set to “0” via the OR gate 337.
Therefore, acceptance of special prize detection switch SW3 is permitted.

End of validity period When the "validity period" of 1.2 seconds passes without any winnings being made to the special winning slot 22, the opening/closing signal T from the timer time creation circuit 32 is activated.
4 (1.2 seconds) is the normal multiplexer 51
The signal appears at the output terminal Z through the channel X0, and is applied to the up counter 43 through the OR gate 45.

The contents of the up counter 43 are incremented by 1 and become "1101".

Selection input A of multiplexers 51 and 52,
B is changed to "10" and channel X0 is switched to X1, so the output Z of the normal multiplexer 51 immediately becomes "0".

Further, the decoder 53 receives the selection input "0001" and sets the output terminal Q1 to "1".

The output "1" of this decoder 53 passes through the OR gate 56, enters the switch input acceptance circuit 33 as the normal operation period signal S4, passes through the inverter 58, and then goes through the NOR gates 335, 336.
The D inputs of FF1 and FF2 are set to "1" through the FF1 and FF2 terminals.

Further, this normal operation period signal S4 opens an AND gate 57 for setting the normal reception circuit 35.

This AND gate 57 receives the timer signal T6 (2.25 seconds) from the timer time generation circuit 32, generates a pulse (normal operation command signal S5), and sends it to the normal operation reception circuit 3 in FIG.
5 to the D flip-flop 352, and the output terminal Q of the flip-flop is set to "1".

This set output passes through OR gate 351 and becomes the D0 input of encoder 41.

Thus, the initial state is returned and the activation switch is turned on.
Completes the operation when SW1 is turned on.

(b) Winning a prize in the second operation winning hole When a prize is won in the second operation winning hole 9 and the second operation switch SW2 is activated, the movable piece 11 as a movable member is operated under the control described below. ,2
The opening/closing operation is performed only once (N times).

The operation of first lighting the upper warning lamp L3 as a display device and then lighting the lower warning lamp L2 is repeated twice, and the whistle sound "po" is also generated twice.

Flashing of warning lamp, opening/closing operation, whistle sound First, when the second operating switch SW2 is activated, the flip-flop FF2 is set through the waveform shaping circuit 332.

The Q output “1” of flip-flop FF2 is
It becomes the topmost input D2 of the encoder 41,
The output code “10” of the encoder 41 is the preset input P3, P of the up counter 43.
2, and the up counter 43 is preset to "1000".

The BCD-decimal decoder 53 decodes the input code "1000" and sets the output terminal Q8 to "1".

This "1" passes through the OR gate 54 and opens the AND gates 63 and 66 of the output circuit 60.

Therefore, the first operating switch SW1 is turned ON.
In the same way as in the above case, the upper warning lamp L3 and the lower warning lamp L2 are sequentially lit for 0.75 seconds.

Also, at the same timing as the lower warning lamp L2, the solenoid SOL is energized and the movable piece 1
1 performs the first opening/closing operation, and the sound generating circuit 80 generates the first whistle sound.

Valid period Since the selection inputs A and B of the normal multiplexer 51 are “00”, the channel Y
0 is selected.

On the other hand, the demultiplexer 44 selects 1 because its selection inputs A and B are "01".
The output "0" of that 1 is given to the terminal ST2 of the normal multiplexer 51 as a strobe signal.

Therefore, the normal multiplexer 51 inputs the timer signal T7 (3.0 seconds) from the timer time generation circuit 32 to the input terminal of its channel Y0.
It enters the "validity period" state in which it expects to be sent.

During this period of 3.0 seconds, the sequential lighting of the upper warning lamp L3 and the lower warning lamp L2, the opening/closing operation of the movable piece 11, and the generation of the whistle sound are performed twice.

During this time, acceptance of the special winning detection switch SW3 is permitted by the switch acceptance control signal SWC, which is the same as when the first operating switch is turned on.

End of Validity Period When the “validity period” of 3.0 seconds passes without a prize being won in the special winning slot 22, the opening/closing signal T7 (3.0 seconds) from the timer time creation circuit 32 will be activated.
Channel Y0 of normal multiplexer 51
appears at the output terminal W via the OR gate 45
It is applied to the up counter 43 through .

The contents of the up counter 43 are incremented by 1,
The output will be “1001”.

Similarly to the case of winning to the first operating prize opening, the selection inputs B and A of the normal multiplexer 51 are changed to "01", and the channel Y1
The output W of the normal multiplexer 51 immediately becomes "0".

In this way, the operation when the operating switch SW2 is turned on is completed.

(c) Winning to the first and second operation winning ports The flip-flop 49 is the first operation switch.
While SW1 is in effect, the second operating switch SW2 is activated.
This is to prevent malfunction when turned on.

While the first operating switch SW1 is active, the demultiplexer 44 has a 1 value of "0", which is input to the D input terminal of the flip-flop 49.

Under this condition, the second operating switch SW2 is turned ON.
Then, triggered by the pulse S8 generated thereby, the flip-flop 49 sets the output terminal Q to the "0" state.

This "0" is input to the NOR gate 431 placed in front of the input terminal A of the demultiplexer 44, and the output of the NOR gate changes from "0" to "1".
becomes.

In other words, the code seen at the inverter 432 connected to the output terminal Q3 of the up counter 43, the NOR gate 431 connected to the output terminal Q2, and the output terminals Q1 and Q0 means that the first operating switch SW1 is active. is forcibly changed from "0000" which means that the second operating switch SW2 is in effect to "0100" which means that the second operating switch SW2 is in effect.

Therefore, the player is required to play the first and second games at the same time.
Even if a prize is won in the operation prize openings 8 and 9, the operation of the second operation switch SW2 with a large profit is guaranteed.

Conversion of special prize mode to gaming state During the valid period when the movable piece 11 is opened and closed once or twice as described above, the movable piece 11
The winning ball enters the special winning hole 22 of the variable winning device 10 using the guide as the winning ball, and the special winning detection switch is activated.
When detected by SW3, it shifts to continuous opening/closing operation with a maximum of 18 times as one cycle.

In order to convert to the gaming state of this "special prize mode" (hereinafter simply referred to as "special prize mode state"), the above-mentioned 1.2 seconds or 3.0 seconds associated with the opening/closing operation of the movable piece 11 are required.
Within the "validity period" of seconds, that is, within the time span when the switch acceptance control signal SW is still "1", the game ball enters the variable winning device 10 and the special winning detection switch SW3 is turned on. is necessary.

Now, when the special prize switch SW3 is turned on,
D flip-flop via waveform shaping circuit 333
FF3 is triggered and its output terminal is set to the "1" state.

The output of FF3 becomes the highest input D1 of the encoder 41, and the output code of the encoder 41 changes from "11" or "10" to "01".

The up counter 43 is preset to "0100".

By presetting the up counter 43, the selection inputs B and A of the demultiplexer 44 are changed to "10", the code input ABCD of the BCD-decimal decoder 53 is changed to "0001", and the selection input A of the special multiplexer 52 is changed to "10". , B remain "00".

Note that the FF 3 and the reference time generating circuit 30 are once reset by the reset signal RE generated at the GS terminal of the encoder 41.

The two outputs "0" of the demultiplexer 44 are applied as strobe signals to the terminals ST1 and ST2 of the special multiplexer 52 to enable the special multiplexer 52.

Since the special multiplexer 52 receives the selection input "00" and selects the channels X0 and Y0, the special multiplexer 52 receives the timer signal T5 (0.75 seconds) from the timer time creation circuit 32 at the input terminal of the channel X0. ) is expected to be sent.

Incidentally, since the switch acceptance control signal SWC at the output terminal 3 of the demultiplexer 44 remains at logic "1", acceptance permission continues to be given to the special winning detection switch SW3.

(a) Blinking of headlights and generation of whistle sound When 2 of the demultiplexer 44 becomes "0" and the output of the inverter 48 becomes H level, the demultiplexer 61 stops,
The light emitting elements LA to LC turn off.

On the other hand, the capacitor C
The terminal voltage of becomes H level, AND gate 6
9 is active.

Therefore, the 0.2 second timer signal T1 is applied to the headlamp L4 drive circuit 608 through the AND gate 69, causing the headlamp L4 as a display device to blink.

This headlamp L4 blinks, for example, about three times.

Thereby, the player can clearly know that the state has been converted to the special prize mode state, and this increases his interest in the pachinko game.

Further, the terminal voltage of the capacitor C is sent to the audio output timing generation circuit 70, and the terminal voltage of the capacitor C is sent to the audio output timing generation circuit 70,
8, the whistle sound generating circuit 81 of the sound generating circuit 80 shown in FIG. 8 is activated.

Therefore, from the speaker 86 "po""po"
Approximately two whistles are heard.

(b) Prohibition of movement of movable piece The decoder 53 decodes the input "0100" and the output terminal Q4 becomes "1".

Since the outputs of output terminals Q0 and Q8 disappear,
The opening/closing operation of the movable piece 11 is temporarily prohibited.

The continuous opening/closing operation of the movable piece 11 is started for the first time when the operation command signal S1 of "1" is generated at the output terminal W of the special multiplexer 52, that is, after 0.75 seconds.

In other words, the movable piece 11 immediately returns to the first state (closed state) regardless of the state of its opening/closing operation.
and remains closed for 0.75 seconds.

Coupled with the flashing of the head lamp L4 at the beginning of this break period, the player is made to clearly perceive the conversion to the special prize mode state.

Note that since the output terminal Q4 of the decoder 53 is "1", the output (count period signal S2) of the inverter 55 connected to the output terminal Q4 disappears, and the AND gate 341 in the count circuit 34 in FIG. is prohibited.

Therefore, the counting function of the counting circuit 34 does not work yet.

(c) Setting the number of rights display The rights number display circuit 36 includes a down counter (right number counter) 361 and a decoder 36.
2. AND gate 363 placed in front of the preset input terminal of the right number counter 361
is open when the content of the right number counter 361 is "0".

AND gate 363 is connected to the output terminal of FF3.

Therefore, when "1" occurs in FF3 at the initial stage when the special winning switch SW3 is turned on, the number of rights counter 361 is preset to "1000" in response to this, and the number of rights display is displayed via the decoder 362. 27 to display "8".

Control of the special mode gaming state After the conversion to the special prize mode state, when the above-mentioned 0.75 seconds, which is the “cycle break”, has elapsed, the movable piece 11
starts opening/closing operations up to 18 times (the 18th time ends in 8.25 seconds).

Here, the "maximum" of 18 times is written because 18 times is a unit cycle of the special prize mode state, 1 cycle, and if a prize is won in the special prize opening 19 during this cycle, for example, the movable This is because even before the 18 opening/closing operations of No. 11 are completed, the cycle is interrupted and the first of the next new cycle is started.

For example, when the special prize switch SW3 is turned ON again after the 12th opening/closing operation and the next cycle starts, the next 13th opening/closing operation will be the 13th opening/closing operation of the previous cycle.
This is not the first time, but the first time of the update cycle.

Further, the number of update cycles, ie, the number of times "q" of exercising rights in the special prize mode state, is allowed up to a maximum of 8 cycles (q=8) in this example.

Therefore, if the maximum number of opening/closing operations of 18 times per cycle is maintained, you can expect 18 x 8 opening/closing operations, but conversely, even if it is the first cycle, there will be no chance of winning the special prize opening 19 during that time. Without it, the cycle is designed to end.

In addition, with this control device, the normal and special winning openings 2
A predetermined number of winning balls for 1 and 22 (10 in this example)
Even if the cycle reaches that point, it is designed to end at that point.

(B) Operation before update After the period of 0.75 seconds during which the headlamp L4 flashes as described above has elapsed, the flip-flop 324 of the timer time creation circuit 32 causes its Q output to fall to the L level, and the Q output to the H level. Switch to .

As a result, the timer time generation circuit 32 generates a timer signal T5 (0.75 seconds).

This timer signal T5 appears at the output terminal Z via the channel X0 of the special multiplexer 52, and is applied to the up counter 43 through the OR gate 45.

The contents of the up counter 43 are incremented by 1,
It becomes “1010”.

Selection inputs B and A of special multiplexer 52
is changed to "01" and switched to channels X1 and Y2.

Input terminal X2 of special multiplexer 52
is the timer signal T from the timer time generation circuit 32.
9 (18 seconds) is expected to occur.

However, since the input terminal Y2 of the special multiplexer 52 is hung at H level, an H level signal (actuation signal S
1) is generated.

Blinking of the lamp inside the case and the lamp on the panel The above operation signal S1 is the lamp inside the case L0
and is sent to the two-input AND gate 62 placed in front of the drive circuit 601 of the panel lamp L1, and the corresponding
Open the AND gate.

Therefore, the output of the inverter 64 applied to the AND gate 62, that is, the timer signal T2 (0.4 seconds) from the timer time creation circuit 32.
The inverted signal of passes through the AND gate 62,
It is applied to the drive circuit 601.

Therefore, the lamp L0 inside the case and the lamp L1 on the panel repeatedly flash every 0.4 seconds.

Generation of Steam Sound The activation signal S1 is sent to the audio output timing generation circuit 70 to open the AND gate 73, and is directly sent to the audio generation circuit 80 to activate the steam whistle generation circuit 81.

The steam whistle sound generation circuit 81 continuously generates steam sounds such as "shyutsu" and "shyutsu" from the speaker 86.

Opening/Closing Operation of the Movable Piece The above-described activation signal S1 is also sent to the AND gate 68 provided in front of the solenoid drive circuit 604 to open the AND gate.

Therefore, the open/close signal T3 from the timer time generation circuit 32 is passed through the AND gate 68.
(0.75 seconds) is applied to the solenoid drive circuit 604.

Therefore, the solenoid SOL is energized for each pulse of 0.75 second width in the opening/closing signal T3, and the movable piece 11 repeats the opening/closing operation continuously up to 18 times in the first cycle. I'm going to go.

Counting Winning Balls While the above opening/closing operation is being performed, many game balls will enter the variable winning device 10 through the movable piece 11.

The total number of winning balls is the count switch SW
4, and it is checked whether it is within a predetermined number.

To be more specific, the winning ball that enters the variable winning device 10, regardless of whether it is a winning ball from the normal winning hole 18 or a winning ball from the special winning hole 19, is determined by the count on the back of the game board. They are gathered into switch SW4 and the count switch is turned on.

Every time count switch SW4 is turned on,
Waveform shaping circuit 334, rising differential circuit 338
Through this, one pulse is input to the winning ball number counting circuit 34.

To be more precise, it becomes the clock input to the winning pitch counter 342 through the AND gate 341.

Since the winning ball number counter 342 has been reset by the reset signal RE generated when the special winning switch SW3 is turned on, the winning ball number counter 342 is sequentially incremented.

An AND gate 343 serving as a decoder connected to the counter 342 detects when the content of the counter 342 reaches decimal "10" and generates a count-up signal S3.

As will be described later, unfortunately, the count-up signal S is not updated without the cycle being updated.
3 occurs, the normal operation reception circuit 35
Through this, the special prize mode state is forcibly switched to the normal gaming state.

Warning at the end of a cycle that has not been updated The total number of winning pitches that occur during the above cycle
Even if there are fewer than 10 pieces, once the 18 opening/closing operations are completed, the special prize mode state will still be forcibly switched to the normal gaming state.

In order to notify the player of the end of this non-updated cycle, in this embodiment, from the start of the 13th opening/closing operation (after 18 seconds), the warning lamps L2 and L3 are alternately blinked, and a warning sound is made. It generates onomatopoeic sounds that imitate the sounds of railroad crossings, such as ``kang'', ``kang'', and ``kang''.

Specifically, when the 12th opening/closing operation is completed, the timer signal T9 (18 seconds) from the timer time generation circuit 32 is sent to the output terminal Z of the special multiplexer 52 through the channel X1.
appears.

This timer signal T9 is applied to the up counter 43 through the OR gate 45 and changes its contents to "0110".

Special multiplexer 52 is channel
1, Y1 is changed to X2, Y2.

Channel Y2 is hung at H level like Y1, so the operation command signal S1 continues to be generated, but channel
The timer signal T is sent to the timer time generation circuit 32.
8 (8.25 seconds) is expected to occur.

The warning is issued for each remaining valid period (8.25 seconds) until the timer signal T8 is generated.

That is, the decoder 53 receives the selection input "0110"
selects the output terminal Q6, and selects the output terminal Q
6 is set to “1”. This selection output “1”
is sent to AND gates 65 and 67, opening both gates.

Therefore, the 0.4 second pulse of the timer signal T2 passes through the AND gate 67 and is connected to the diode D.
4 to the drive circuit 603, first turning on the upper warning lamp L3 for 0.4 seconds.

When this 0.4 seconds wide pulse falls, then
A pulse with a width of 0.4 seconds, which is an inverted signal of the timer signal T2, is generated in the inverter 64, and this pulse is applied to the drive circuit 602 through the AND gate 65 and the diode D2, thereby lighting the lower warning lamp L2 for 0.4 seconds.

Thereafter, the upper warning lamp L3 and the lower warning lamp L2 flash alternately.

Moreover, the game board 1 and the decoder 53
“1” at the output terminal 6 is sent to the audio output timing generation circuit 70, and the AND gate 73
While the signal is opened, the sound is sent as is to the sound generation circuit 80, and the level crossing sound generation circuit 82 is activated.

Therefore, the take-off sounds created by the take-off sound generation circuit 82 are generated from the speaker 86.

End of Predetermined Cycle Time If 8.25 seconds elapse without any winning in the special winning slot 22 despite the above warning, the normal operation acceptance circuit 35 is set.

More specifically, a timer signal T8 (8.25 seconds) is generated in the timer time generation circuit 32, which appears at the output terminal W of the special multiplexer 52 through the channel X2, and sets the output terminal W to "1".

This "1" is sent to the up counter 43 through the OR gate 45, setting the content of the counter to "0111".

Since the selection inputs B and A of the special multiplexer 52 change from "10" to "11", the channels are switched from channels X2, Y2 to X3, Y3. Since the channels X3 and Y3 are each fixed to "0", the output terminals Z and W of the special multiplexer 52 are immediately set to "0".
falls to

As a result of the disappearance of the operation command signal S1 that had been generated at the output terminal W until then, the opening/closing operation of the movable piece 11 is stopped, the lamp inside the case L0 and the lamp L1 on the panel are turned off, and the generation of steam noise is also stopped.

Further, when the up counter 43 becomes "0111", the selection input of the decoder 53 becomes "0111", so that "1" as the cycle end signal S7 is generated at the output terminal Q7 of the decoder 53.

This cycle end signal S7 is passed through the OR gate 56 as the normal operation period signal S4.
It is sent to AND gate 57.

The AND gate 57 receives the timer signal T6 (2.25 seconds) input to one of its input terminals, generates the normal operation command signal S5, and outputs the eighth
The output terminal Q of the D flip-flop 352 of the normal operation receiving circuit 35 shown in the figure is set to the "1" state.

This set output passes through OR gate 351 and becomes the D0 input of encoder 41.

Therefore, the up counter 43 is returned to the initial state "0000", the Q2 output terminal of the demultiplexer 44 becomes "1", the counter 361 of the right number display circuit 36 is cleared, and the right number display 27 is cleared. is “8” to “0”
Return to

In this way, all the circuits are returned to their initial state immediately after power-on.

Note that the cycle end signal S7 is also applied to the clock input terminal of the D flip-flop 352 of the normal operation acceptance circuit 35;
When the final cycle signal ES, which will be described later, is generated in the right count display circuit 36 and the D input of the D flip-flop 352 is "1", regardless of the timer signal T6 (2.25 seconds),
This is to invert the state of the output terminal Q of the D flip-flop 352 to "1".

(b) Cycle update Under the restriction that the total number of winning balls that occur during the above cycle is up to 10, and before the above 18 opening/closing operations are completed, the special winning hole 22 If there is a winning ball, it will be updated to a new cycle.

If you enter the special winning slot again during this new cycle, it will be updated to the next cycle with the same operation as above, and if not, when the winning ball number counter 342 counts the number of pulses "10", , the circuit returns to its initial state.

Now, when the special winning switch SW3 is turned on at any time during the first cycle, "1" is generated in FF3 of the switch reception circuit 33, and the increment circuit 40 and the number of rights display are incremented.

Cycle break In response to “1” of the above FF3, the encoder 41 of the step circuit 40 outputs Q1, Q.
0 becomes "01" and the up counter 43 is again preset to "0100".

At this time, the contents of the winning ball number counter 342 are cleared by the reset signal RE.

Even after presetting, the demultiplexer 44 still selects only 2 as "0", but
The selection inputs B and A of the special multiplexer 52 are switched from "01" or "10" to "00".

Therefore, the special multiplexer 52 returns to the channel X0, X0 selection state.

Therefore, similar to the transition to the above-described special prize mode state, "cycle separation" operations such as blinking the head lamp L4 and temporarily prohibiting the opening/closing operation of the movable piece are performed.

Changing the number of rights display “1” in FF3 is input to the clock input terminal of the number of rights counter 361, the content of the number of rights counter 361 is decremented by 1, and the number of rights display 43 is switched from “8” to “7”. Change.

This causes the first cycle to be interrupted and the second cycle to be interrupted.
This means that the right number of times display 27 has been updated, and the display content of the right number of times display 27 indicates the remaining number of times that the rights can be updated.

Visually displaying the contents of the counter in this way is interesting for players.

(c) After the 2nd cycle In the 2nd cycle and after, special winning slot 2 will be opened again.
The same goes for the case where you win the second prize, and the same operation is repeated.

At this time, each update point, that is, the break between each cycle, is clearly perceived by the player by the action of closing the movable piece 11 for 0.75 seconds, the blinking of the headlamp L4, and the generation of the whistle sound during that time.

Further, regarding each cycle, when the opening/closing operation reaches the end of the 13th cycle or later, a warning is given to the player by flashing warning lamps L3 and L2 and generating a railroad crossing sound.

Incidentally, each time the special winning switch SW3 detects a winning ball and the cycle is updated, the number of rights counter 361 temporarily decreases its contents.

Fortunately, if it is updated to the eighth and final cycle, a total of 18 opening/closing operations promised in that cycle will be performed, and the special prize state will be completed.

In other words, in the middle of the 7th cycle, special prize opening 22
When a prize is won, the content of the number of rights counter 361 becomes "1", and the number of rights display 27 indicates that the number of remaining times becomes "1", and at the same time, the decoder 364 connected to the counter changes the value of the down counter 361. Detects “0001” and generates the final cycle signal ES.

This final cycle signal ES sets the D input terminal of the D flip-flop 352 of the normal operation receiving circuit 35 to "1".

This puts the D flip-flop 352 in a state in which it expects a clock input.

Further, the final cycle signal ES enters the switch input reception circuit 33, and is sent to the inverter 365,
The D input of FF3 is set to “1” via the NOR gate 337.

Therefore, in the subsequent eighth cycle (final cycle), FF3 no longer accepts the ON signal of special winning switch SW3.

Under the above conditions, a total of 18 opening/closing operations as promised in the 8th cycle are performed.

Then, when the 18th opening/closing operation is completed, more precisely 27 seconds after the start of counting in the 8th cycle, the special multiplexer 52
The output terminals Z and W of the decoder 53 each become "0", and a cycle end signal S7 is generated at the output terminal Q7 of the decoder 53.

The cycle end signal S7 sets the D flip-flop 352 of the normal reception circuit 35, and its output terminal Q becomes "1".

In this way, the entire circuit system returns to its initial state.

The pachinko machine changes from the special prize mode state to the normal game state.

Forced switching to the normal gaming state If one cycle ends without being updated, that is, if 27 seconds have passed after the start of counting and a total of 18 opening/closing operations have been completed, the output of the decoder 53 The D flip-flop 3 of the normal reception circuit 35 is activated by the cycle end signal S7 generated at the terminal Q7.
52 is set, and its output terminal Q becomes "1".

Therefore, as described above, the entire circuit system is returned to the initial state, the special prize mode state is forcibly canceled, and the normal gaming state is returned.

Therefore, from now on, the first and second specific winning openings 8,
The special prize state cannot be reached unless a series of operations from winning number 9 is performed.

This disadvantageous situation for the player is as described above.
This occurs because there are no prizes entered into the special prize opening 22 after that during one cycle of 18 times as one unit.

On the other hand, while performing the opening/closing operation, the movable piece 1
1, a large number of game balls win in the variable winning device 10, and when the total number of winning balls reaches 10, the content of the winning ball number counter 342 becomes "10".

For this reason, the number of balls connected to the winning ball counter 342 is
A count-up signal S3 is generated in the decoder consisting of the AND gate 231, and the normal operation acceptance circuit 3
Through the OR gate 226 of 5, the operation step circuit 4
The 0 encoder 41 generates "00".

The up counter 43 of the operation advance circuit 40 becomes "0000", and as described above, the entire circuit system is returned to its initial state, and the special prize mode state is also forcibly canceled.

Note that, as described above, an example of the embodiment of the present invention is shown using hardware, but it can also be configured using software.

(Effects of the Invention) As described above, the pachinko machine of the present invention converts the movable member of the variable winning device M times into the second state where it is easier for the game ball to win each time a winning is made to the first operating winning opening. At this time, the display device (warning lamp)
lights up M times, and the sound generator generates sound M times.

Also, each time you win a prize in the second operating prize opening,
The movable member of the variable prize winning device is changed N times to the second state in which it is easy to win a game ball, and at this time, the display means (warning lamp) is lit N times and the sound is generated from the sound generating device N times.

Therefore, the player can both visually and audibly
It is possible to easily and reliably determine whether a prize has been won in the first or second operation winning port.

In addition, the first and second report lamps are used as display means.
In the case where the player is divided into warning lamps, since the second warning lamp lights up next to the first warning lamp, interest in the pachinko game is increased.

[Brief explanation of the drawing]

Fig. 1 is a front view showing an embodiment of the pachinko machine of the present invention, Fig. 2 is a perspective view of the variable winning device with the movable piece in the first state, and Fig. 3 shows the movable piece in the second state. A perspective view of the variable winning device, FIG. 4 is a diagram showing the relationship between the winning collection gutter on the back of the game board and the variable winning device, FIG. 5 is a perspective view showing the movable piece of the variable winning device and its drive mechanism, Figure 6 is a sectional view of the variable prize winning device, Figures 7, 8 and 9 are circuit diagrams of the control device of the pachinko machine shown in Figure 1, and Figure 10 is a detailed diagram of its reference time generation circuit. It is. DESCRIPTION OF SYMBOLS 1...Game board, 4...Game area, 8...First operating winning port, 9...Second operating winning port, 10...Variable winning device, 11...Movable piece (movable member), 18...
...Concave chamber, 19...Diversion shelf branching member, 21...Normal winning opening, 22...Special winning opening, 30...Reference time generation section (timer generation means), 31...Clock generation circuit, 32...Timer Time creation circuit, 33...
Input reception circuit, 34... Winning ball counting circuit, 3
5... Normal operation reception circuit, 50... Timing generation circuit (timing control means), 70... Audio output timing generation circuit, 60... Audio generation circuit,
L0... Lamp inside the case (display means), L1...
Panel lamp (display means), L2... Warning lamp (display means), 3... Warning lamp (display means), L
4... Head lamp (display means), SOL... Electromagnetic solenoid (electrical drive source), LA, LB, LC...
Light emitting element, SW1...first operating switch, SW2
...Second operating switch, SW3...Special winning detection switch, SW4...Count switch, T1~
T9...Timer signal.

Claims (1)

[Scope of Claims] 1. A variable prize winning device having a movable member in a gaming area of a game board that can be converted by an electric drive source between a first state in which it does not accept a batted ball and a second state in which it easily accepts a batted ball; In a pachinko machine that is provided with first and second operating winning ports for activating a variable winning device, and further provided with a special winning hole in the variable winning device, and a control device that controls the sound generating device, the display device, and the electric drive source, and the control device is movable after the detection output of the first operating switch belonging to the first operating winning hole. A first timer means regulating the effective time during which the member is in the second state M times, and an effective time during which the movable member is in the second state N times after the detection output of the second operating switch belonging to the second operating winning opening. and a timing control means for receiving a signal from the timer generating means and operating an electric drive source, a display device, and an audio generating device, By the timing control means, when the first operating switch is activated under the normal gaming state, the initial state is shifted from the initial state to the first output state for an effective time determined by the first timer means, and the electric drive source, display device, When the sound generating device is activated and the second operating switch is activated under normal gaming conditions, the initial state is shifted from the initial state to the second output state for an effective time determined by the second timer means, and the electric drive source, The display device and the sound generating device are activated, and if a prize is entered into the special prize slot within the valid time period during which the second state conversion operation is performed M times or N times, the second state for the special prize mode gaming state is entered. 3 output state, and the movable member is configured to perform continuous conversion operations many times based on a timer signal corresponding to the special prize mode gaming state from the timer generating means.