JPS58134476A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS58134476A JPS58134476A JP1850182A JP1850182A JPS58134476A JP S58134476 A JPS58134476 A JP S58134476A JP 1850182 A JP1850182 A JP 1850182A JP 1850182 A JP1850182 A JP 1850182A JP S58134476 A JPS58134476 A JP S58134476A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate electrode
- film
- thin film
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011521 glass Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 23
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000011368 organic material Substances 0.000 claims description 2
- 239000003921 oil Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 42
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229910001415 sodium ion Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 239000011651 chromium Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Abstract
Description
【発明の詳細な説明】
この発明は特性向上を図った１１膜トランジスタに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an 11-film transistor with improved characteristics.
従来のこの種の薄膜トランジスタとして第１図および第
２図に示すものがあった。Conventional thin film transistors of this type include those shown in FIGS. 1 and 2.
図において（１）はガラス基板、（２）は写真製版工程
により、ガラス基板（１）上面の所定位置に形成された
クロム（Ｑからなるゲート電極、（３）はこのゲート電
極の上面および両側面を覆い、両側端がガラス基板上面
に延在したシリコン窒化膜からなるゲート絶縁層で、そ
の厚みは約８０００λである。（４）はグロー放電によ
り、ゲート絶縁層（３）上面に形成されたアモルファス
シリコン１ｍ１（５） （６）はクロム（Ｃｒ）ｔ？こ
のアモルファスシリコン層（４）上面に蒸着、写真製版
工程を経て形成されたソースおよびドレイン電極で、上
記ゲート電極（２）をはさむようセ対向して配設された
ものである。（７）はこれらソースおよびドレイン電極
（６） （６） ＊びにアモルファスシリコン層（４）
上面を覆うように形成されたシリコン窒化膜からなる絶
縁膜である。In the figure, (1) is a glass substrate, (2) is a gate electrode made of chromium (Q) formed at a predetermined position on the top surface of the glass substrate (1) by a photolithography process, and (3) is the top surface and both sides of this gate electrode. The gate insulating layer is made of a silicon nitride film that covers the entire surface and extends on both sides to the top surface of the glass substrate, and has a thickness of approximately 8000λ.(4) is formed on the top surface of the gate insulating layer (3) by glow discharge. 1 m1 of amorphous silicon (5) (6) is chromium (Cr)t? Source and drain electrodes are formed on the top surface of this amorphous silicon layer (4) through a photolithography process, sandwiching the gate electrode (2). (7) are these source and drain electrodes (6) (6) and the amorphous silicon layer (4).
This is an insulating film made of a silicon nitride film formed to cover the upper surface.
次にこの株に構成された薄膜トランジスタの動作につい
て説明する。まず、ゲート電極（２）にＯｖを、トレイ
ン・ソース［１ｉｉｉｉ （６） （５）間ニ１０Ｖｉ
ノｌＩ圧ヲ印加する。この時アモルファスシリコン層（
４）はバンドキャップが通常のシリコンに比べて広いた
め光があたっても、キャリアが励起される確率は低い。Next, the operation of the thin film transistor constructed in this stock will be explained. First, Ov is applied to the gate electrode (2), and 10Vi is applied between the train and source [1iii (6) (5).
Apply pressure. At this time, the amorphous silicon layer (
4) has a wider band gap than normal silicon, so even when exposed to light, the probability that carriers will be excited is low.
従って光をあてた状態名も抵抗は非常に高く、電流はほ
とんど流れないものである。この時のドレイン・ソース
電極（６） （５）間の抵抗をＯＦＦ抵抗という。次に
ケート電極（２）に正電圧を６〜２０Ｖ＠度加えると、
ゲート絶縁層（３）を介してアモルファスシリコン層（
４）の界面に電界が加えられ、チャネルが開いてドレイ
ン・ソース電極（６） （６）間が導通できるようｉζ
なり電流が流れは、しめるものである。この時のドレイ
ン・ソース電極（６） （５）間の抵抗をＯＮ抵抗とい
う。Therefore, when exposed to light, the resistance is extremely high and almost no current flows. The resistance between the drain and source electrodes (6) and (5) at this time is called OFF resistance. Next, when applying a positive voltage of 6 to 20 V @ degree to the gate electrode (2),
An amorphous silicon layer (
4), an electric field is applied to the interface of
The flow of current is what slows it down. The resistance between the drain and source electrodes (6) and (5) at this time is called ON resistance.
しかるに、この様に構成された薄膜トランジスタにあっ
ては、アモルファスシリコンＪ！（４）はそのバンドギ
ャップが広いため暗電流は少なく、高いＯＦＦ抵抗を得
られるが、モビリティ−が小さいためＯＮ抵抗も高（０
８時の電流が小さくなる欠点がある。そξで、０８時の
電流を多くするためＯＮ抵抗を小さくするために、少な
くともソース・ドレイン電極（６） （６）間に位置す
るアモルファスシリコン層（４）を、連・、続発振のレ
ーザー光や電子線等で再結晶化して大きなグレインの多
結晶とし、モビリティ−を高め”Ｃ”ＯＮ電流を多くと
るようにしたものが提案されている。However, in a thin film transistor configured in this way, amorphous silicon J! (4) has a wide band gap, so the dark current is small and a high OFF resistance can be obtained, but because the mobility is small, the ON resistance is also high (0
There is a drawback that the current at 8 o'clock is small. Therefore, in order to increase the current at 08 and reduce the ON resistance, at least the amorphous silicon layer (4) located between the source and drain electrodes (6) (6) is heated using a continuous oscillation laser. It has been proposed that polycrystals with large grains are obtained by recrystallization using light, electron beams, etc. to increase mobility and increase the "C" ON current.
しかし、この提案された薄膜トランジスタは、ＯＮ抵抗
を下げ、ＯＦＦ抵抗を高くできたが、表示デバイス例え
ば、透過型のカラー液晶ディスプレイにおける液晶マト
リックスの駆動用トランジスタ等に利用する場合には、
光のあたる状態で使用されるため、アモルファスシリコ
ン層（４）の再結晶化された多結晶シリコン層は通常の
シリコンと同じバンドギャップをもつためアモルファス
シリコンに比べて格段に光励起されるキャリア数が多く
、暗電流が無視できないほど流れるので、ＯＦＦ抵抗を
高くできなくなり、表示デバイスには利用でき憂ζくい
という欠点が生じた。However, although this proposed thin film transistor was able to lower the ON resistance and increase the OFF resistance, when used in a display device such as a transistor for driving a liquid crystal matrix in a transmissive color liquid crystal display,
Since it is used in the presence of light, the recrystallized polycrystalline silicon layer of the amorphous silicon layer (4) has the same band gap as ordinary silicon, so the number of photoexcited carriers is significantly greater than that of amorphous silicon. However, since a non-negligible amount of dark current flows, it is impossible to increase the OFF resistance, resulting in a drawback that it is difficult to use it for display devices.
この発明は上記した点に鑑みてなされたものであり、少
なくともゲート電極上に対向するアモルファスシリコン
層の上方に絶縁膜を介して遮光層を設け、この遮光層と
ゲート電極とにより、アモルファスシリコン層への光を
遮蔽するようにして、光の当る状態で使用されたとして
もＯＦＦ抵抗を高く維持できるようにした仁とを目的と
するものである。This invention has been made in view of the above-mentioned points, and includes providing a light-shielding layer above the amorphous silicon layer facing at least the gate electrode with an insulating film interposed therebetween. The object of the present invention is to provide a device that blocks light from entering the device and maintains a high OFF resistance even when used in a state where it is exposed to light.
以下にこの発明の一実施例を第８図（ａ）〜（ｄ）に基
づいて説明する。第８図（ａ）〜（ｄ）はこの発明の一
実施例となる薄膜トランジスタを製造する際の工程図で
ある。まず第８図（ａ）Ｉζ示すように、ガラス板（１
ａ）の上面及び下面両面暑ζ、このガラス板（ｌａ）か
らナトリウム等可脚イオンが放出されるのを防ぐために
、プラズマＣＶＤＩζより約２０００人の厚さの窒化膜
（ｌｂ） （ｌｂ）を形成して基板（１）を構成する。An embodiment of the present invention will be described below based on FIGS. 8(a) to 8(d). FIGS. 8(a) to 8(d) are process diagrams for manufacturing a thin film transistor according to an embodiment of the present invention. First, as shown in FIG. 8(a) Iζ, a glass plate (1
a) In order to prevent the release of legible ions such as sodium from this glass plate (la), a nitride film (lb) with a thickness of about 2,000 people is coated from the plasma CVDIζ. The substrate (1) is formed by forming the substrate (1).
次に、第８図（ｂ）に示すように写真製版工程により基
板（１）上所定位置番とクロム（Ｃｒ ）からなるゲー
ト電極（りを形成し、さらに、このゲート電極（２）お
よび基板（１）上に５ｏｏｏ人の窒化膜からなるゲート
絶縁層（３）を形成する。その後第８図（ｃ）に示すよ
うに、ゲート電極（２）上のゲート絶縁層（３）上書ζ
約５０００人の厚さのアモルファスシリコン層（４）を
形成し、このアモルファスシリコン層（４）上にクロム
（Ｃｒ ）を蒸着し、写真製版工程を経て、ゲート電極
（２）をはさむように対向してソースおよびドレイン電
極（６）情）を形成スる。ξの時、アモルファスシリコ
ン層−）に、連続発振のアルゴンレーザ光を照射して、
少な曵ともゲージ電極切対向の１カのアモルファスシリ
コン層（４）を再結晶化された多結晶シリコン層に変換
しても良い。このように多結晶シリコン層に変換した場
合には、ゲート電極（２）に正電圧を加えた際に生じる
チャネル部でのキャリアのモビリティ−を上げることか
で赤、ＯＮ時の電流を多く取ることがでキ、シかも、ト
ランジスタの幅を多結晶シリコンに変換しなかったもの
に比べ格段にせまくでき、微細化にとって有効なものと
なる。Next, as shown in FIG. 8(b), a gate electrode made of chromium (Cr) is formed at a predetermined position on the substrate (1) by a photolithography process, and then this gate electrode (2) and the substrate are formed. (1) A gate insulating layer (3) made of a nitride film of 500 mm is formed on the gate electrode (2).Then, as shown in FIG. 8(c), the gate insulating layer (3) on the gate electrode (2) is overwritten.
An amorphous silicon layer (4) with a thickness of approximately 5000 nm is formed, chromium (Cr) is vapor deposited on this amorphous silicon layer (4), and through a photolithography process, the gate electrode (2) is sandwiched between the layers facing each other. Then, source and drain electrodes (6) are formed. When ξ, the amorphous silicon layer -) is irradiated with continuous wave argon laser light,
At least one amorphous silicon layer (4) facing the gauge electrode may be converted into a recrystallized polycrystalline silicon layer. In the case of converting to a polycrystalline silicon layer in this way, a large current can be obtained when the gate electrode (2) is turned on by increasing the mobility of carriers in the channel region that occurs when a positive voltage is applied to the gate electrode (2). However, the width of the transistor can be made much narrower than that without converting to polycrystalline silicon, making it effective for miniaturization.
次にアモルファスシリコン層（４）、ソースおよびドレ
イン電極（５）（６）、ならびにゲート絶縁膜（３）上
にシリコン窒化膜からなる絶縁膜（７）を形成し、この
眉間膜（７）上にアルミニウム（ＡＪ）を蒸着し、写真
製版工程を経費なくともゲート電極（８）に対向する位
置に遮光層（８）を形成する。その後、この遮光層（８
）および絶縁膜（７）上にＰＩＱをコートすることによ
って保護膜（９）を形成し、第８図（ｄ）に示される薄
膜トランジスタを得るものである。Next, an insulating film (7) made of a silicon nitride film is formed on the amorphous silicon layer (4), the source and drain electrodes (5) and (6), and the gate insulating film (3), and the glabellar film (7) is Aluminum (AJ) is vapor-deposited on the substrate, and a light-shielding layer (8) is formed at a position facing the gate electrode (8) without the expense of a photolithography process. After that, this light shielding layer (8
) and the insulating film (7) to form a protective film (9) by coating PIQ to obtain the thin film transistor shown in FIG. 8(d).
この様に構成された薄膜トランジスタにあっては、その
動作が第１図および＠２図に示すものと同様に動作する
うえに、アモルファスシリコン層（４）の下部はクロム
からなるゲート電極（２）Ｉζより、その上部はアルミ
ニウムからなる遮光層（８）によりアモルファスシリコ
ン層（４）に入る光を連断することができ、この薄膜ト
ランジスタを強い光にさらしながら、動作させても高い
ＯＦＦ抵抗が得られるという利点があるものである。In the thin film transistor configured in this way, its operation is similar to that shown in Figures 1 and 2, and the lower part of the amorphous silicon layer (4) is a gate electrode (2) made of chromium. From Iζ, the light-shielding layer (8) made of aluminum on the upper part can block the light entering the amorphous silicon layer (4), and even if this thin film transistor is operated while being exposed to strong light, a high OFF resistance can be obtained. This has the advantage that it can be used.
また、アモルファスシリコン層（４）の少なくともゲー
ト電極（りに対向する部分を多結晶シリコンに変換した
ものとすれば、高いＯＦＦ抵抗が得られるうえに低いＯ
Ｎ抵抗を同時に得られる利点があり、表示デバイス、特
に透過型のカラー液晶ディスプレイにおける液晶マトリ
ックスの駆動用トランジスタとして最適なものである。Furthermore, if at least the portion of the amorphous silicon layer (4) facing the gate electrode (4) is converted to polycrystalline silicon, high OFF resistance and low O
It has the advantage that N resistance can be obtained at the same time, and is optimal as a transistor for driving a liquid crystal matrix in a display device, especially a transmissive color liquid crystal display.
なお、上記実′施例では基板（１）としてガラス板と窒
化膜と７構成したものとしたが、他の絶縁体、あるいは
半導体でも良く、ゲート絶縁層（３）として１：
酸化シリコン膜あるいは窒化シリコン膜としても・１．
。In the above embodiment, the substrate (1) is composed of a glass plate and a nitride film, but other insulators or semiconductors may be used, and the gate insulating layer (3) is a silicon oxide film or a silicon oxide film. As a silicon nitride film: 1.
.
良いものである。 ・
また、上記実施例では遮光層（８）をアルミニウムで形
成したが、アルミニウム以外の金属、可視または近赤外
を通さない有機物、あるいは半導体で−多酸しても同様
の効果を奏するものである。It's good. - In addition, in the above example, the light shielding layer (8) was formed of aluminum, but the same effect can be achieved by using a metal other than aluminum, an organic material that does not transmit visible or near infrared rays, or a polyacid semiconductor. be.
この発明は以上述べた様に、基板上にゲート電極と、ア
モルファスシリコン層を介してゲート電極をはさむよう
に対向して配設されたソースおよびドレイン電極を備え
た薄膜トランジスタにおいて、少なくともゲート電極に
対向するアモルファスシリコン層上に絶縁膜を介して遮
光層を形成したので、遮光層とゲート電極とにより、ア
モルファスシリコン層への光を遮蔽することができ、光
の当る状態で使用してもトランジスタのＯＦＦ抵抗を高
い状態で維持でき、性能の低下をきたさないという効果
がある。As described above, the present invention provides a thin film transistor that includes a gate electrode on a substrate, and source and drain electrodes that are disposed opposite to each other with the gate electrode interposed through an amorphous silicon layer. Since a light-shielding layer is formed on the amorphous silicon layer via an insulating film, the light-shielding layer and the gate electrode can block light from entering the amorphous silicon layer, and the transistor will remain stable even when used in a state where it is exposed to light. This has the effect that the OFF resistance can be maintained in a high state and the performance does not deteriorate.
第１図および１１２図は従来のＭＯＳ ）ランジスタ構
造を有する薄膜トランジスタを示す要部断面図および要
部平面図、第８図（ａ）〜（ｄ）は仁の発明の一実施例
となる薄膜トランジスタの製造方法を工程順に示す要部
断面図である。
図において（１）は基板、（２）はゲート電極、（３）
はゲート絶縁層、（４）はアモルファスシリコン層 （
５）はソース電極、（６）はドレイン電極、（７）は絶
縁膜、（８）は遮光膜である。
なお各図中同一符号は同一、又は相当部分を示す。
代理人 葛舒信−
第１図
ル
第２図
第３図
（４）
’：Ｃｄ）1 and 112 are a cross-sectional view and a plan view of a main part of a thin film transistor having a conventional MOS transistor structure, and FIGS. FIG. 3 is a cross-sectional view of main parts showing the manufacturing method in order of steps. In the figure, (1) is the substrate, (2) is the gate electrode, (3)
is the gate insulating layer, (4) is the amorphous silicon layer (
5) is a source electrode, (6) is a drain electrode, (7) is an insulating film, and (8) is a light shielding film. Note that the same reference numerals in each figure indicate the same or equivalent parts. Agent Ge Shuxin - Figure 1 Figure 2 Figure 3 (4) ':Cd)
Claims (1)
形成されたゲート電極、このゲート電極上にゲート絶縁
膜を介して形成されたアモルファスシリコン層、このア
モルファスシリコンＪＩ上に形成され、上記ゲート電極
をはさみ対向して配設されたソースおよびドレイン電極
、少なくとも上記ゲート電極に対向するアモルファスシ
リコン層上に絶縁膜を介して形成された遮光層を備えた
薄膜トランジスタ。 （２）アモルファスシリコン層を、少なくともその一部
が多結晶に変換されたものとしたことを特徴とする特許
請求の範囲１ｉ１項記載の薄膜トランジスタ。 （３）基板をガラス板とこのガラス板の上面および下面
両面に施された窒化膜とで構成したものとしたことを特
徴とする特許請求の範囲第１項又は第２項記載の薄膜ト
ランジスタ。 （４）遮光層を金属層とした仁とを特徴とする特許請求
の範囲第１項ないし第８項のいずれかに記載の薄膜トラ
ンジスタ。 （ｆ、）遮光層を可視または近赤外を通さない有機−と
したことを特徴とする特許請求の範１１１ｔｉ１項ない
し第８項のいずれかに記載Ｏｉｌ＆にトランジスタ。 （６）遮光層を半導体としたことを特徴とする特許請求
の範囲第１項ないし第８項のいずれかに記載の薄膜トラ
ンジスタ。[Claims] (1) A substrate made of a semiconductor or an insulator, a gate electrode formed on this substrate, an amorphous silicon layer formed on this gate electrode with a gate insulating film interposed therebetween, and this amorphous silicon JI layer. A thin film transistor comprising: a source and a drain electrode disposed to face each other with the gate electrode in between; and a light shielding layer formed on at least an amorphous silicon layer facing the gate electrode with an insulating film interposed therebetween. (2) The thin film transistor according to claim 1i1, wherein at least a part of the amorphous silicon layer is converted to polycrystalline. (3) The thin film transistor according to claim 1 or 2, wherein the substrate is composed of a glass plate and a nitride film applied to both the upper and lower surfaces of the glass plate. (4) The thin film transistor according to any one of claims 1 to 8, characterized in that the light shielding layer is a metal layer. (f) The oil transistor according to any one of claims 1 to 8, wherein the light shielding layer is made of an organic material that does not transmit visible or near infrared light. (6) The thin film transistor according to any one of claims 1 to 8, wherein the light shielding layer is made of a semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1850182A JPS58134476A (en) | 1982-02-05 | 1982-02-05 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1850182A JPS58134476A (en) | 1982-02-05 | 1982-02-05 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58134476A true JPS58134476A (en) | 1983-08-10 |
Family
ID=11973369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1850182A Pending JPS58134476A (en) | 1982-02-05 | 1982-02-05 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58134476A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134470A (en) * | 1983-12-22 | 1985-07-17 | Seiko Epson Corp | Semiconductor device |
| JPS61145818A (en) * | 1984-12-20 | 1986-07-03 | Sony Corp | Heat processing method for semiconductor thin film |
| JPH02263474A (en) * | 1983-08-19 | 1990-10-26 | Semiconductor Energy Lab Co Ltd | Insulated gate type field effect transistor |
| JPH0750420A (en) * | 1994-03-31 | 1995-02-21 | Semiconductor Energy Lab Co Ltd | Manufacturing method of insulating gate type field-effect transistor |
| JPH07131033A (en) * | 1994-03-31 | 1995-05-19 | Semiconductor Energy Lab Co Ltd | Insulated gate fet transistor |
| JP2000156504A (en) * | 1998-09-04 | 2000-06-06 | Semiconductor Energy Lab Co Ltd | Semiconductor device with semiconductor circuit consisting of semiconductor element and its manufacture |
| US6794681B2 (en) * | 1997-03-18 | 2004-09-21 | Semiconductor Energy Laboratory Co., Ltd. | Substrate of semiconductor device and fabrication method thereof as well as semiconductor device and fabrication method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS567480A (en) * | 1979-06-29 | 1981-01-26 | Mitsubishi Electric Corp | Film transistor |
| JPS5623780A (en) * | 1979-07-31 | 1981-03-06 | Sharp Corp | Manufacture of thin film transistor |
-
1982
- 1982-02-05 JP JP1850182A patent/JPS58134476A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS567480A (en) * | 1979-06-29 | 1981-01-26 | Mitsubishi Electric Corp | Film transistor |
| JPS5623780A (en) * | 1979-07-31 | 1981-03-06 | Sharp Corp | Manufacture of thin film transistor |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02263474A (en) * | 1983-08-19 | 1990-10-26 | Semiconductor Energy Lab Co Ltd | Insulated gate type field effect transistor |
| JPS60134470A (en) * | 1983-12-22 | 1985-07-17 | Seiko Epson Corp | Semiconductor device |
| JPS61145818A (en) * | 1984-12-20 | 1986-07-03 | Sony Corp | Heat processing method for semiconductor thin film |
| JPH07118444B2 (en) * | 1984-12-20 | 1995-12-18 | ソニー株式会社 | Heat treatment method for semiconductor thin film |
| JPH0750420A (en) * | 1994-03-31 | 1995-02-21 | Semiconductor Energy Lab Co Ltd | Manufacturing method of insulating gate type field-effect transistor |
| JPH07131033A (en) * | 1994-03-31 | 1995-05-19 | Semiconductor Energy Lab Co Ltd | Insulated gate fet transistor |
| US6794681B2 (en) * | 1997-03-18 | 2004-09-21 | Semiconductor Energy Laboratory Co., Ltd. | Substrate of semiconductor device and fabrication method thereof as well as semiconductor device and fabrication method thereof |
| US7141462B2 (en) | 1997-03-18 | 2006-11-28 | Semiconductor Energy Laboratory Co., Ltd. | Substrate of semiconductor device and fabrication method thereof as well as semiconductor device and fabrication method thereof |
| JP2000156504A (en) * | 1998-09-04 | 2000-06-06 | Semiconductor Energy Lab Co Ltd | Semiconductor device with semiconductor circuit consisting of semiconductor element and its manufacture |
| JP4493741B2 (en) * | 1998-09-04 | 2010-06-30 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
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