JPS58129617A - Program starting system - Google Patents
Program starting systemInfo
- Publication number
- JPS58129617A JPS58129617A JP57013011A JP1301182A JPS58129617A JP S58129617 A JPS58129617 A JP S58129617A JP 57013011 A JP57013011 A JP 57013011A JP 1301182 A JP1301182 A JP 1301182A JP S58129617 A JPS58129617 A JP S58129617A
- Authority
- JP
- Japan
- Prior art keywords
- register
- program
- factor
- starting
- activation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
+8) 発明の技術分野
本発明はマイクロコンビエータで各種のプログラムを使
9て試験1111IIl計611〜を行う場合、簡便に
各樵10グラムを起動出来るプログラム起動方式に関す
る。Detailed Description of the Invention +8) Technical Field of the Invention The present invention relates to a program starting method that can easily start each woodcutter 10g when performing tests 1111II1 to 611 using various programs in a micro combinator.
(b) 従来技術と関軸点
従来はマイクロコンビエータで各種の10グラムを使り
て試験制御計−1等を行う場合は要因別に各種1關グツ
ム及び割込み処理用の10グラムをメモリ#C記憶して
おき、マイクロプロセッサ(以下CPUと略称する)の
有する電源オン又はマニアルリセット端子より1tCP
Uをリセットし、割込み端子より、使用するプログラム
を設定し、割込み処理を、して試験制御針#11等を行
ってい九〇このため割込み処理用のプログラムが必要で
あると共に試験制御計#1等の要因別プログラムを増加
したい場合は、割9込み処理用の7oグラムを変更する
必要がある欠点がありた・間該CPUをり七ットする場
合電源オンかマニアルリセットかの判別が出来ない欠点
がありた0
(C) 発明の目的
本発明の目的は上記の欠点をなくするために試験側i&
11!を態勢に使用する璧因別プログラムの割込み処理
プログラムを必要とせす、かつ電源オンの場合はこの場
合に必要とする10グラムのみで処理出米又上記壺因別
1■グラムを増加したい場合藺阜に対処出来る7゛四グ
ラム起動方式の提供にある0
(dl 発明の構成
本発明は上記の目的を達成するためにマイクロ1aセツ
サ及び処理を遂行するプログラムを配憶する記憶部を持
りマイクルコンビエータシステムにおいて、6抛のプロ
グラムの起#IJJを指令する欽pays聯zqスイッ
チを有する操作部と、各スイッチの操作により、該マイ
クロプロセッサにリセット4!号を送るオア回路1.及
び各スイッチ操作に対応した起動JI!!因レジスタ、
及び起動4j!因解除レジスタを具備し、該スイッチの
操作により該オア回路を介し、骸ツイタ簡プロセッサを
初期化し、初期プログラムを起動させ、又該スイッチに
対応した起動要因レジスタを設定すれば、販マイクロプ
ロセッサは、該初期グログ2ムによりM起動要因レジス
タの設定内容を読込み俊該起動蟹因解除レジスタを介し
該起動要因レジスタをリセットすると共に起動要因に対
i6したプログラムを起動し処理することを特命とする
10クラム起動方式である・
(e) 発明の実施例
以下本発明の一実施例に′)自重に従りて説明する・8
1図は本発明のvM施例のマイクロコンビニ−声のブロ
ック図、菖2−#i本発明の実施例の70チヤート、第
3−は本発明の実施例の起−要因レジスタのフラグをえ
てる場所の割付は−である・図中1はオアー路、2は起
動要因レジスタ、3は起動費因#除レジスタ、4はCP
tJ、5#iメ毫り、6 aチー fi Ax、5WI
−8VWnkfiXイツチ、POWONは亀−をオンし
た時の個号入力端子、賦MIIKHIII計ll1l尋
に使用する10グシムは一〇要因別にメそり5に格納さ
れている。又電源オンの@号入力端子pot ON及
び各要因別起動簀求スイッチ5WI−8WnFiオア回
路l及び起動要因レジスタ2に接続されている・起動要
因レジスタ2は第30に示す如く起動要因別にフラグを
たてる位置が割付けられており、起動要求があれば該当
する起*喪因の所の2ラグをたてるよう忙なうている◎
父オア回路lとCPU4の間はり七ット侶号−7で接続
されてhる@
今壺因別記−要求スイッチ例えばEIWIをオンすゐと
、オア回路l及びリセットgs号mrを介してリセッ)
41号がCPU4に入力すると共に起動要因レジスタ2
の軌3−のSWI起動の所の7ラグを立てゐ・これによ
りCPU4#′i初期化され初期プログラムが起動し一
データパス6を介し起動要因レジスタ2の8W1起動の
72グを絖塚p要氷内谷を知シ、起動解除レジスタ3を
介して起動要因レジスタ2をリセットすると共に、起動
要因を解析しメモリ5内にあると8WIK対応し九1謬
ダラムを起動して目的の処理をけう。(b) Prior art and relevant points Conventionally, when performing test control meter-1 etc. using 10 grams of each type in a micro combinator, 10 grams of each type and 10 grams for interrupt processing were stored in memory #C for each factor. 1tCP from the power-on or manual reset terminal of the microprocessor (hereinafter abbreviated as CPU).
Reset U, set the program to be used from the interrupt terminal, perform interrupt processing, and perform test control needle #11, etc. If you want to increase the number of programs for each factor, such as, there is a drawback that it is necessary to change the 7ogram for interrupt processing.・When resetting the CPU, it is not possible to determine whether the power is turned on or a manual reset is performed. (C) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by the testing side i&
11! If you want to use an interrupt handling program for a specific program, and the power is on, in this case you only need 10g to handle the process.Also, if you want to increase the above 1g to To achieve the above object, the present invention provides a micro 1a setter and a memory section for storing a program for performing processing. In the combiator system, there is an operation unit having a pays link switch that commands the start of 6 programs, an OR circuit 1 that sends a reset signal to the microprocessor by operating each switch, and each switch. Startup JI!! cause register corresponding to operation,
And launch 4j! If the microprocessor is equipped with a cause cancellation register, and the operation of the switch initializes the Mukuro Twitter processor through the OR circuit, starts the initial program, and sets the activation cause register corresponding to the switch, the sales microprocessor can be used. , the special mission is to read the setting contents of the M activation factor register by the initial log 2m, reset the activation factor register via the activation cause cancellation register, and start and process the program corresponding to the activation factor. (e) Embodiment of the Invention Below, an embodiment of the present invention will be explained according to its own weight.
Figure 1 is a block diagram of the micro convenience store voice of the vM embodiment of the present invention, Figure 2 is the 70th chart of the embodiment of the present invention, and Figure 3 is the flag of the cause factor register of the embodiment of the present invention. The allocation of the locations is - in the figure. 1 is the OR path, 2 is the activation factor register, 3 is the activation cost factor # exclusion register, and 4 is the CP.
tJ, 5#i mail, 6 achi fi Ax, 5WI
-8VWnkfiX, POWON is the number input terminal when the turtle is turned on, and the 10 gums used for the total of 10 times are stored in the memory 5 for each of the 10 factors. In addition, it is connected to the @ input terminal pot ON when the power is turned on, the activation request switch 5WI-8WnFi OR circuit l for each factor, and the activation factor register 2.The activation factor register 2 sets flags for each activation factor as shown in No. 30. The position where it will be raised is assigned, and if there is a startup request, it will be busy to set up the 2 lags of the corresponding cause * ◎
The father OR circuit 1 and the CPU 4 are connected by the 7th node 7. When the request switch, for example EIWI, is turned on, the reset occurs via the OR circuit 1 and the reset gs node MR. )
41 is input to the CPU 4 and the activation factor register 2
Set the 7 lag at the SWI startup in trajectory 3- This initializes the CPU 4#'i, starts the initial program, and sends the 72 lag at the 8W1 activation of the activation factor register 2 via the data path 6. Resetting the activation factor register 2 via the activation cancellation register 3, it analyzes the activation factor and if it is in the memory 5, supports 8WIK and activates the 91-year-old Daram to perform the desired process. Keu.
本発明の場合は、試験制御計尋を行うための要因別にス
イッチSWI〜5WII及び起動要因レジスタ2があり
、こtlKよりCPU4Fi起Vl景因を鰯識してこt
’lK対応したメモリ5内の10クラムを起動すればよ
いので、とtlに便用する割込み処理プログラムは必要
なくなる。又11飾オンの場合4起111+要因レジス
タ2によりCPU4は1鉱出来るのでこの場合に処理す
る必要なプログラムのみメモリ5に起憶漣しておけばよ
く、このプログラムは簡単になる。In the case of the present invention, there are switches SWI to 5WII and activation factor register 2 for each factor for performing test control calculation, and from this tlK, you can identify the cause of CPU4Fi-induced Vl.
Since it is only necessary to activate 10 crumbs in the memory 5 corresponding to 'lK, there is no need for an interrupt processing program that is useful for and tl. In addition, in the case of 11 decorations, the CPU 4 can be used by 1 due to 4 111 + factor register 2, so only the program necessary to process in this case needs to be stored in the memory 5, and this program becomes simple.
又#L験制御計5111等の場合の処城壺因が増加した
場合はスイッチを増加し、起動要因レジスタ2の内容を
追加しこのためのプログラムをメモリ5に配憶させれば
よ(、従来性りていた割込み処理プログラムの変更等の
如く10ダラムのf!1!!は必要としない。Also, if the number of triggers increases in the case of the #L test controller 5111, etc., increase the number of switches, add the contents of the activation factor register 2, and store the program for this in the memory 5. There is no need to change the f!1!! of 10 Durhams, which is required in the past, such as changing the interrupt processing program.
(f) 発明の効果
以上詳細に説明した如く本発−によnはマイクロコンビ
ニー−を使用し試験側@)1を副等を打なう場合、これ
◆に使用する割込み処理10グツムが不要で又電紛オン
の場合もこの場合に必要とするプログラムのみ作成して
おけばよくプログラムが簡単になり、又試験制御針側等
の場合の処理要因の増加要求の場合簡単に対処出来る効
果がある◎4.1面の簡単な1112Ill+
第1−は本発明の実施例のマイクロコンビエータのブロ
ック図、第21は本発明の実施例のフローチャート、第
3図は本発明の実o翫例の起動要因レジスタのフラグを
たてる場合の割付は図である〇図中1けオア回路、2#
′i起動普因レジスタ%3は起IIII要因解除レジス
タ、4はCPU、5はメモリ、6けデータバス、7はリ
セット信号綜、SWI〜swnはスイッチ、powor
iaX&をオンした時の01号入力1子である。(f) Effects of the Invention As explained in detail above, when the test side @) 1 is subtitled using the microconvenience store, the interrupt processing 10 used for this ◆ is Even if it is not necessary and the electric spray is on, the program can be simplified by creating only the program required in this case, and the effect that it can be easily handled when there is an increase in processing factors such as on the test control needle side, etc. There is a simple 1112Ill+ on the 4.1 page. 1st - is a block diagram of a micro combinator according to an embodiment of the present invention, 21st is a flowchart of an embodiment of the present invention, and 3rd is an actual example of the present invention. The assignment when setting the flag of the activation factor register is shown in the figure. In the figure, 1 digit OR circuit, 2 #
'i startup cause register %3 is startup III cause release register, 4 is CPU, 5 is memory, 6-digit data bus, 7 is reset signal line, SWI~swn are switches, power
This is No. 01 input 1 child when iaX& is turned on.
迅1図 基2図 晃3 図Jin 1 figure Base 2 diagram Akira 3 figure
Claims (1)
憶する記憶部を持りマイクΩコンピュータシステムにお
いて、各釉プログラムの起動を指令するスイッチを有す
る一作部と、各スイッチの操作により、該マイクロ10
セツサにリセット信号を送るオア(ロ)へ及び各スイッ
チ操作に対応した起動要因レジスタ、及び起勧賛因解除
レジスタを具備し、該スイッチの操作により該オア回路
を介し、該マイクロ10セツサを初期化し、初期プロ該
初期プログラムにより該勘動豐因レジスタの設足内谷を
読込み後該起動要因解除レジスタを介し該起動畳因レジ
スタをリセットすると共に超動要因に対応したプログラ
ムを起動し処理をすることを特徴とする10グラム起勧
方式。In a microphone computer system having a microprocessor and a storage unit for storing programs for processing, there is a part having a switch for instructing the activation of each glaze program, and the micro 10 is activated by operating each switch.
It is equipped with an OR (b) that sends a reset signal to the setter, an activation cause register corresponding to each switch operation, and an activation cause release register, and the operation of the switch initializes the micro 10 setter via the OR circuit. After reading the initial value of the activation factor register by the initial program, the activation factor register is reset via the activation factor cancellation register, and the program corresponding to the hypermotion factor is activated and processing is performed. The 10-gram promotion method is characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57013011A JPS58129617A (en) | 1982-01-29 | 1982-01-29 | Program starting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57013011A JPS58129617A (en) | 1982-01-29 | 1982-01-29 | Program starting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58129617A true JPS58129617A (en) | 1983-08-02 |
Family
ID=11821222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57013011A Pending JPS58129617A (en) | 1982-01-29 | 1982-01-29 | Program starting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58129617A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62102332A (en) * | 1985-10-29 | 1987-05-12 | Nec Home Electronics Ltd | Data processor equipped with microprocessor |
US9532552B2 (en) | 2012-04-13 | 2017-01-03 | Viscon B.V. | Device and system for processing of eggs, such as vaccination or a vacuum suction or grabber based pick up |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5578318A (en) * | 1978-12-11 | 1980-06-12 | Fujitsu Ltd | Program loading processing system |
JPS5592916A (en) * | 1979-01-01 | 1980-07-14 | Toshiba Corp | Program controller |
JPS5645947B1 (en) * | 1971-05-04 | 1981-10-29 |
-
1982
- 1982-01-29 JP JP57013011A patent/JPS58129617A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5645947B1 (en) * | 1971-05-04 | 1981-10-29 | ||
JPS5578318A (en) * | 1978-12-11 | 1980-06-12 | Fujitsu Ltd | Program loading processing system |
JPS5592916A (en) * | 1979-01-01 | 1980-07-14 | Toshiba Corp | Program controller |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62102332A (en) * | 1985-10-29 | 1987-05-12 | Nec Home Electronics Ltd | Data processor equipped with microprocessor |
US9532552B2 (en) | 2012-04-13 | 2017-01-03 | Viscon B.V. | Device and system for processing of eggs, such as vaccination or a vacuum suction or grabber based pick up |
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