JPS62102332A - Data processor equipped with microprocessor - Google Patents

Abstract

PURPOSE:To save the capacity of a ROM by varying the high-order digit bit pat of a ROM address to a specific value corresponding to a task select signal and carrying out a task. CONSTITUTION:A data processor which is utilized as a function testing device, etc., for a data communication terminal equipment selects one of plural testing tasks in the ROM 2 with a switch 11, the high-order digit bit of an address from an MPU 1 is varied by a circuit 12 to the specific value according to the task select signal of the switch, and peripheral devices 6, 7, 8... which are used for the execution of the task are put in operation by a selecting circuit 13. Then, a reset signal is supplied to the MPU 1 through an OR gate 16 from a circuit 14 every time the task select signal is generated with the switch 11, and then an interruption signal generated by the device 6... selected by the circuit 13 is supplied selectively to the interruption input terminal of the MPU 1 to execute the task.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device equipped with a microprocessor.

2. Description of the Related Art Data processing devices equipped with microprocessors are also used as functional test devices for data communication terminal devices.

In such a functional test device, a test program that describes a predetermined procedure for a functional test is stored in the ROM, and after connecting its input/output section to the device under test, the test program is executed from the first address in the ROM. A functional test is performed by executing the function.

Such test programs are usually created as a set of multiple independent tasks for different test items, and are executed sequentially.

Problems to be Solved by the Invention In the above-mentioned functional test equipment, an RO that stores an O8 with advanced functions such as a large computer system is used.
Since there is no M capacity, task creators themselves must control switching between tasks and make coordination between tasks regarding allocation of resources to be used.

For this reason, there are problems in that it takes time to create a test program, and a considerable portion of the ROM capacity is used to control switching between tasks.

In particular, when multiple people share tasks for different test items, each person must understand them in order to maintain consistency with the tasks being created by others, which requires extra effort. The problem is that you have to spend a lot of money.

Structure of the Invention Means for Solving the Problems The data processing device of the present invention which solves the problems of the prior art described above has a microprocessor that receives a reset signal and starts executing a task stored at a predetermined address in a ROM. It assumes a processor.

This processing device has an RO where multiple tasks are stored.
M, a task selection signal generator that issues a task selection signal to select one of the multiple tasks stored in this ROM to be executed, and a high-order ROM address output from the microprocessor. and an address changing unit that changes the bit to a predetermined value according to the task selection signal.

Furthermore, this processing device includes a use circuit selection unit that enables a circuit used for the execution of a selected task to operate according to the task selection signal, and a reset unit that supplies a reset signal to the microprocessor every time the task selection signal is generated. It is configured to easily and quickly switch tasks and their used resources using hardware.

Embodiment FIG. 1 is a block diagram showing the configuration of a portion of a testing device for a data communication terminal device according to an embodiment of the present invention that is related to this embodiment.

This test equipment is connected to a microprocessor (MPU), a ROM 2 in which multiple test tasks are stored, a RAM 3 used as a working area during test execution, an address bus 4, a data bus 5, and the device under test. It is equipped with peripheral devices 6, 7, 8, etc. such as input/output devices.

Furthermore, this test device includes a task selection signal generation switch 11 that issues a task selection signal for selecting one of the plurality of test tasks stored in the ROM 2 to be executed, and an output from the microprocessor. The address change circuit 12 changes the upper bits of the address to be selected to a predetermined value according to the task selection signal, and the peripheral devices 6, 7, 8, etc. used by the selected task for execution according to the task selection signal. It also includes a device selection circuit 13 that enables the device to operate.

Furthermore, this processing device includes a reset signal generation circuit 14 that supplies a reset signal to the reset terminal (R3T) of the microprocessor 1 via an OR gate 16 each time a task selection signal is issued from the switch 11, and a device selection circuit to be used. The microprocessor 1 includes an interrupt selection circuit 15 that selectively supplies an interrupt signal generated by a peripheral device selected by the microprocessor 1 to an interrupt input terminal (INT) of the microprocessor 1.

As illustrated in Figure 2, ROM2 stores tasks A, B, and C that describe the execution procedures for three types of test items.
Starting addresses ADRA, ADRB and ADRC respectively
It is stored in the area starting from .

When the operator wants this testing device to execute test task A, he generates a selection signal for task A by closing the task selection switch Sa. The address change circuit 12 receiving this task selection signal changes the address bus 4
By opening the upper bit address line in the microprocessor 1, the address output from the microprocessor 1 is directly supplied to the ROM 2 without any modification.

This task selection signal is also supplied to the device selection circuit 13 and the interrupt selection circuit 15. The device selection circuit 13 that receives this task selection signal selects a plurality of peripheral devices 6, 7 .
8..., only those used for executing task A are selected and made operational. Further, the interrupt selection circuit 15 receiving the task selection signal selects the peripheral device 6.7.8.
. . , only the interrupt signal issued from the one used for executing task A is selected and supplied to the interrupt input terminal INT of the microprocessor 1.

On the other hand, the reset signal generation circuit 14 detects the closing of the task selection switch Sa and generates a reset signal. The microprocessor 1 that receives the reset signal via the OR gate 16 resets various built-in registers, and then starts executing task A starting from the first address in the ROM 2.

The above reset operation is performed using the existing reset signal input terminal 17.
This is similar to the case where a reset signal is received from the OR gate 16. That is, when the reset input terminal (RST) becomes active, the microprocessor 1 disables internal register interrupts and releases the address bus and data bus. When the input signal subsequently becomes inactive, the microprocessor 1 starts executing the task starting from the first address of the ROM 2.

When the test apparatus is to execute test task B, the task selection switch sb is closed and a task B selection signal is generated. Upon receiving this task selection signal, the address change circuit 12 fixes the upper bit address line in the address bus 4 to a predetermined high or low state, thereby changing the range of ROM addresses output from the microprocessor 1 starting from ADRB. Change to task B storage area.

The device selection circuit 13 that receives this task B selection signal
The interrupt selection circuit 15 connects a plurality of peripheral devices 6, 7, 8, and
. . , which are used for executing task B, are made operational, and only the interrupt signal issued from the selected peripheral device is supplied to the interrupt input terminal INT of the microprocessor 1.

On the other hand, a reset signal is generated from the reset signal generation circuit 14, and upon receiving the reset signal, the microprocessor 1 resets various built-in registers and then starts executing task A starting from the first address in the ROM 2. in fact,
By changing the address supplied from the microprocessor 1 to the ROM 2 by the address changing circuit 12, task B starting from ADRB is executed.

Similarly, when this test device is to execute test task C, the task selection switch Sc is closed, and the address change circuit 12 receives this, causing the upper bit address line in the address bus 4 to go high or low. is fixed at a predetermined state value, and the range of addresses output from microprocessor 1 is changed to the storage area of task C starting from ADRC.

Device selection circuit 13 that receives this task C selection signal
and the interrupt selection circuit 15, a plurality of peripheral devices 6, 7
．． 8, . At the same time, the microprocessor 1 receiving the reset signal from the reset signal generation circuit 14 starts executing task A starting from the first address in the ROMZ, but the address supplied from the microprocessor 1 to the ROM 2 is
2, task C starting from ADRC is actually executed.

Although the configuration in which the interrupt selection circuit 15 is added has been exemplified above, the interrupt selection circuit 15 can be omitted if no interrupt signal is issued from a peripheral device other than the one selected by the device selection circuit 13.

Further, by changing the RAM address in the address change circuit 12 based on the task selection signal, it is also possible to allocate a working area to each task.

Effects of the Invention As explained in detail above, the data processing device of the present invention adds a simple task selection function, an address change function, and a used circuit selection function to the reset function unique to a microprocessor, thereby improving the control of tasks and their execution. Since it is configured to select the equipment to be used using hardware, it is possible to control switching between tasks, which was previously done by the task creator,
There is no need for coordination between tasks regarding the allocation of used resources, etc., the time required to create a test program is significantly reduced, and the ROM capacity conventionally required for controlling switching between tasks is also significantly reduced.

In particular, even when multiple people are sharing tasks for different test items, each person can create their own tasks without considering consistency with the tasks being created by others.
This will reduce the amount of time it takes to create it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing apparatus according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram for explaining the operation of FIG. 1. 1...Microprocessor, 2...ROM, 3...RA
M, 4...address bus, 5...data bus, 6
, 7.8...Peripheral device, 11...Task selection switch, 12...Address change circuit, 13...Use bag W selection circuit, 14...Reset signal generation circuit, 15...Interrupt selection circuit. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (1)

[Claims] A processing device including a microprocessor that receives a reset signal and starts executing a task stored at a predetermined address in a ROM, comprising: a ROM in which a plurality of tasks are stored; a task selection signal generation unit that generates a selection signal for selecting one of the plurality of stored tasks to be executed; and a task selection signal generation unit that generates a selection signal for selecting one of the stored tasks to be executed; an address changing section that changes the address to a predetermined value according to the task selection signal; a circuit selection section that enables a circuit used for the execution of the selected task to operate according to the task selection signal; 1. A data processing device equipped with a microprocessor, comprising: a reset signal generating section that supplies a reset signal to the microprocessor.