KR920001358Y1 - Rom for resetting of micro processor system - Google Patents

Abstract

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Description

ROM changer for resetting microprocessor systems

1 is a circuit diagram showing a connection state of a microprocessor and a reset ROM according to the present invention.

2 is a detailed circuit diagram of the present invention.

(A)-(f) of FIG. 3 is a signal waveform diagram of each part of the circuit of this invention.

The present invention relates to a microprocessor system, and in particular, when a reset signal is applied to a microprocessor, a reset ROM device for a reset of a microprocessor system configured to execute a program embedded by applying a predetermined signal to a reset ROM. It is about.

In a conventional microprocessor system, when a reset signal is input to a microprocessor from a reset signal generator, the microprocessor outputs address and control signals for calling a reset ROM.

These signals are decoded by the decoding unit to call the reset ROM, thereby executing a predetermined program embedded in the reset ROM.

However, such a conventional device has a reset ROM always occupying a portion of the memory map, and thus the memory area during normal operation cannot be used. The disadvantage is that the memory capacity that can be accessed by the microprocessor becomes smaller.

The present invention provides a switching ROM such that the reset ROM of the microprocessor executes a program only during the reset operation and is removed from the memory map after the reset operation. The memory area occupied by this memory can be reused to increase the memory utilization of the microprocessor.

As shown in FIG. 1, the present invention comprises a reset signal generator 1, a decoding unit 2, a switching circuit unit 3, and a reset ROM 4. As shown in FIG.

The reset signal generator 1 resets the reset signal. And the decoding unit 2 receives and decodes the control signal and the address of the microprocessor and selects the chip selection signal. Generates.

here Is the selection signal corresponding to the part where the reset ROM is executed on the memory map and the same memory map in the normal state after performing the reset routine. Is a select signal corresponding to another part of the normal state after the reset routine is performed.

The key point of the present invention is the switching circuit section 3 is a reset signal , Chip select signal ( ) And a chip select signal which is selected after the reset in common with the map of the reset ROM 4 Generates.

That is, the switching circuit unit 3 is ( In the reset routine, the chip select signal Signal, in normal state after reset, ) Has the function to switch.

So, for example, if 1Mbytes is required for the reset routine in a processor system that can access 16Mbytes, only 1Mbytes can be used for the steady state program in the conventional method, whereas in the present invention, the 1Mbytes memory area used for the reset routine is in the normal state. It can be used again as a program area in.

In the figure, SW is a reset switch, 101, 102 is a resistor, 103 is a diode, 104 is a capacitor, 105 and 106 is an inverter, 301 is a T flip-flop, 302 is an inverter, and 303 and 304 are OR gates.

The effect of the present invention is that reset signal SW is turned on as shown in Figs. Is output to reset terminal of flip-flop 301 Since the low signal is applied to the flip-flop 301 is reset.

Therefore, the reset mode signal which is the output (Q) signal of the flip-flop 301 at this moment Is low (see Figures 3 (a) and (d)) and the reset mode signal is low. Is inverted by the inverter 302 so that the high signal is inputted to one side of the OR gate 303, so that the output of the OR gate 303 is Silver chip select signal Regardless of the state, the signal becomes high and reset mode signal ( Chip selection signal is continued while) is low. Will invalidate.

In addition, the reset mode signal which is the output Q of the flip-flop 301. Is also input to one side of the OR gate 304 and is currently low (FIG. 3 (d)), so the chip select signal input to the other side of the OR gate 304 is Select signal of the reset ROM 4 as an output of the OR gate 304 )

Reset mode signal When is low level, chip select signal Is masked to a high level and the reset ROM (4) has a chip select signal on the memory map. It exists as an area corresponding to.

(B) of Figure 3 (b)

Then, the program embedded in the reset ROM 4 is executed. After the execution of the program, the microprocessor selects a chip select signal. Chip selection signal by calling an area other than the address of the chip selected by Validate

At this moment, this chip select signal Is applied to the clock terminal CP of the flip-flop 301, and thus the reset mode signal which is the output Q of the flip-flop 301. Will output a high signal.

Therefore, this high state reset mode signal Is applied to one side of the OR gate 304 to select the chip selection signal Will be masked.

That is, the output signal of the OR gate 304 Is chip select signal The chip select signal is maintained at all times regardless of the state of At the same time, the high reset mode signal Is inverted by the inverter 302 so that the low signal is applied to one input of the OR gate 303, and at this time, the chip select signal that is the other input of the OR gate 303 Output through OR gate Therefore, the chip select signal corresponding to the memory area of the reset ROM 4 after the reset program is executed. do.

That is, the microprocessor selects the chip select signal. After the call to the selected memory area, the reset ROM 4 is removed from the memory map and a chip having the same memory area is used instead. It is chosen by.

As described above, according to the present invention, the reset ROM of the microprocessor system is used only for the reset time. Selected by the signal to run the program, after which it is removed from the memory map and the corresponding portion of the memory map Since the normal routine is selected by selecting, the memory area required to perform the operation of the microprocessor is expanded accordingly.

Claims (1)

(Correction) The reset signal from the reset signal generator 1 and the decoder 2, respectively. ) And chip select signal Is input and chip select signal of reset ROM 4 And a chip select signal common to the memory map of the reset ROM 4 and corresponding to this memory map area after the reset. The reset signal which is the output of the reset signal generator 1 in the switching circuit section 3 for outputting Temporary reset signal Chip select signal to the clock terminal CP of the T flip-flop 301 input to the Is the reset mode signal that is input and its output (Q) The chip select signal on one side through the inverter 302 Is input to the other side of the OR gate 303 to which the chip is input and at the same time the chip selection signal Input to the other side of the OR gate 304 is input to one side, the output of the OR gate 304 Chip select terminal of the reset ROM 4 ), And the chip select signal at the output of the OR gate 303 ROM changer for a microprocessor system configured to output power.