JPS5839191A - Initializing system for peculiar data for circuit designating identification - Google Patents

Abstract

PURPOSE:To initialize automatically mounting position information of mounted packages when power is turned on at the operation start, by providing a latch circuit, where mounting position information for circuit designating identification is stored, in each package. CONSTITUTION:When the power of an exchange is turned on, all FFs of respective packages PKG0, PKG1,- are turned on and are set initially, and a central processing unit CC transmits an initialization timing signal ID to all packages. At this time, only an AND gate ANF of the package having the highest priority is turned on to open a gate circuit G. The first peculiar data for circuit designating identification transmitted from the unit CC is stored in a latch DL of the package PKG0 through the gate G, and simultaneously, the FF is inverted. Then, an AND gate ANL of the package PKG1 having the next highest priority level is turned on, and next peculiar data for circuit designating identification is taken into the data latch circuit DL of the packag PKG1. Hereafter, peculiar data are given to packages having lower priority levels successively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for initially setting mounting position information as unique data for circuit designation identification unique to each mounted truck or cage when power is turned on to start operation in circuit designation of a time division switch. The main purpose of this is to simplify and increase the accuracy of work by automating initial settings.

Conventionally, in a time division switch, as shown in Figure 1, each pack mino has a unique data setting switch S for circuit designation identification.
W For example, since the installation position information of each A' cage is manually initialized as unique data for circuit designation identification using a dip switch, etc., the settings become complicated as the number of cages accommodated increases. This method has the drawback of increasing the possibility of duplication, missing numbers, or excessive setting errors.

Tsuchimoto's invention solves these problems by providing a data latch circuit in each package that stores the mounting position information as unique data for circuit designation identification, and using the mounting position information from the central processing unit for circuit designation identification. A detailed description of the present invention, which is characterized in that mounting position information is automatically assigned, sent, set, and stored from the central processing unit at the time of operation start/startup when the power is turned on as identification unique data.

FIG. 1 is a diagram illustrating a method used in a conventional time division switch. In the figure, CC is the central processing unit, SW is the unique data setting switch for circuit designation identification, and C
The OM compares the unique data for circuit designation identification initialized by the unique data setting switch SW for circuit designation identification with the circuit designation data from the central processing unit CC, and sends circuit designation information SLT only when they match. Comparison circuits for
This is a data bus for exchanging various data connected to the common between GIs. Is each J here? Unique data setting switch SW for circuit designation identification provided in the package
When there are a large number of packages containing dip switches, etc., manual initial settings are complicated and can easily result in incorrect settings such as missing numbers, duplicates, or excessive settings.The present invention solves this problem. It is.

Now, FIG. 2 is a professional diagram explaining one embodiment of the present invention, and the DL stores mounting position information specific to each mounting base and cage as unique data for circuit designation identification. data latch circuit, G is a data acquisition dirt circuit for controlling the timing to initialize the unique data for circuit designation identification given to each mother and cage to the medata latch circuit DL, and BUS is the center circuit. Processing device C
C and installed mother, cage PKGOe PKGI t PK
G2, . . . A data bus for exchanging various data, COM, connected to the common between G2, . This is a comparison circuit that determines whether or not they match, and when they match, generates circuit designation information SLT indicating that the package is designated as a circuit.

PO is the initial setting timing signal ID sent from the central processing unit CC in synchronization with the mounting position information of each arm and cage is sent to the data/4 bus as unique data for circuit designation identification for initial setting. Each thread forming the path, wires commonly connected to the cage, cage designated lead, FF
sends the mounting position information from the central processing unit CC to the data controller and circuit DL.

ANF, ANL is a flip-frog that intercepts the data import instruction control signal DRC to determine the data import order (priority) between cages and cages.
is an AND gate that shares one of the inputs with the central processing unit CC
The initial setting timing signal ID is provided through the package designation lead po' from the package designation lead po', and one of the other inputs is the output of the flip 70 in the own package. Further AN
L is the third input that is higher in the data acquisition order (priority), and by guiding the output of 7"FF" to the cage designated lead P1, When the package initializes the unique data for circuit designation identification, data import is prohibited for the package. The data acquisition instruction control signal DRC output from the AND gates ANF and ANL is input to the control input terminal of the data acquisition f-) circuit G, and is also input to the flip-flop FF, and sent out from the central processing unit CC. At the same time, the position information is initially set in the gator latch circuit DL as circuit designation identification data, and at the same time, the 7 lip flop fFF is inverted.

In such a configuration, it is assumed that all the flip-flops FF of each shoe cage are initially set to ON at the time of startup when the power is turned on to the exchange.
Data bus B from central processing unit CC to i +
The mounting position information created and assigned by the central processing unit CC as unique data for circuit designation identification via the US, and the initial setting timing of the circuit designation identification unique data via the package designation lead po, are sent, and the data is captured at this time. AND gate AN of the package with the highest order (priority)
Only F is its own FF, and Pflozzo FF's initial set output (priority signal that suppresses the lower order) PRIOR opens the side and outputs data capture instruction control signal DR.
Since C is input to the data acquisition dirt circuit G, the unique data for circuit designation identification is initially set to the data L and CH circuits DL, and for all other packages, the AND gate ANL is set.
Since the third input of the AND circuit ANL is a prohibition output, the output of the immediately upper 7-lip flow, fFF, which generates the priority No. 1 PRIOR that suppresses the lower order, is output, so the output of the AND circuit ANL is a data import instruction control signal. Since the DRC cannot be output, the data latch circuit DL does not store the mounting position information as the unique data for circuit designation identification of the first successful circuit that has arrived on the data bus BUS1.

Here, since the flipflop 7'FF to which the data fetching instruction control signal DRC is input is only the d'package PKGO, which has the highest data fetching order (priority), only the flipflop 7'FF of this flipflop is inverted. , 2nd place and lower A' Package PKG 1st place 7 lip flops will not be reversed. Data import order (priority) The highest-ranked package PKGO's AND-DART ANF is self-freak, and the reversal of NO-FLO-7'FF closes the r-t. Only the second-highest priority package PKGI is AND-GO)
The prohibition input of the third input of ANL is canceled and the prohibition input of the third input of ANL continues, so the next input is continued. In the cycle, the data capture control signal DRC is generated only in the shoe cage PKGI with the second priority, and the second signal sent by the central processing unit CC is generated to the data capture circuit DL of the cage and the cage PKGI. As soon as the mounting position data is initialized, the output of the no-flow 7' FF is inverted, and on the other hand, the initial settings for the data la and chi circuits DL are also changed as described above. Frog FF is also not inverted.In other words, the initial setting of the second priority shoe cage PKGI and the third priority shoe cage PK (not shown) are performed.
Preparations for the initial settings of G2 have been made. Furthermore, in the next cycle, in the same way, the initial setting of the cage PKG2 with the third priority (not shown) and the initial setting preparation of the cage PKG3 with the fourth priority (not shown) are performed. It will be done.

In this way, the unique data for circuit designation identification is initialized in the data latch circuit 1 DL for the mother cages at the top of the priority order and the mother cages at the lower priority order.

At the stage of circuit designation while the exchange is in operation, the central processing unit CC sends out mounting position data of the corresponding shoe cage as circuit designation information via the data bus BUS. In each case, the sent circuit designation information and the unique data for circuit designation identification already latched in its own data latch circuit DL are compared in the comparator circuit COM, and both data match. Comparison circuit COM
Karaso・ri.

Circuit designation information SLT indicating that the cage has received circuit designation
occurs. Since the following functions of the exchange are not directly related to the gist of the present invention, their explanation will be omitted.

As is clear from the above description, according to the present invention, by providing the order setting circuit and the latch circuit with a simple configuration, it is possible to initialize the unique data for circuit designation identification for each of the four packages at the time of starting up the switch. This is an extremely significant feature that eliminates misconfigurations such as missing numbers, duplicates, and excessive number assignments that occur during cumbersome manual setups that are performed automatically, and ensures that startup initial setups that match the system specifications are easily performed. be effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional manual initialization method of unique data for circuit designation identification, and FIG. 2 is a block diagram of a method of initializing unique data for circuit designation identification according to the present invention. CC...center Processing device, BUS...data bus, P
o, Pl...Rikkage designated lead, PKGO, PK
C.I. PKG2・Rear cage, G...Dart circuit for data acquisition, DL...Data latch circuit, COM...Comparison circuit, FF...Fritsunoflo, Zo, ANF, ANL
...AND circuit, DRC...data import instruction control signal, ■D...initial setting timing signal, PRIOR・
・Priority signal to suppress lower order, SLT ・Circuit specification information.

Claims (1)

[Claims] When specifying a circuit, circuit specification information is sent from the central processing unit (CC) via a data bus (BUS) commonly connected to all mother packages, and circuit specification identification information is already stored uniquely for each block and cage. Compare the circuit designation identification unique data and - in the comparison circuit and find that they match. In the designated circuit designation method, a data latch that is connected to a data acquisition dirt circuit (G) and a comparison circuit (COM) whose data input terminals are connected to a common, respectively, and latches the circuit designation identification specific data. The output of the circuit (DL) '4゜, which generates a control signal that prohibits the data acquisition of the 742 cases with lower priority, is the first input terminal. The second input terminal is connected to each wire, the cage designated lead (PO) is connected to the cage in common, and the third input terminal is connected to the flip-flop FF of the cage.
and f-), the output ends of which are connected to the input terminals of the FRI, NOFLO, and 7°, respectively, and the control input terminal of the data acquisition f-) circuit, and the switching system At the time of starting up, only when mounting position information is sequentially assigned and output from the data output terminal of the central processing unit (CC) via the data bus (BUS) as unique data for circuit designation identification, the gloss , by sending an initial setting timing signal to the cage designation lead (PO), it is possible to change the priority from the cage with the higher priority to the cage with the lower priority. A system for initializing unique data for circuit designation identification, characterized in that information on the mounting position of the mother package is sequentially initialized as unique data for circuit designation identification in the data latch circuit of the package.