JPS5812051A - Control processing system - Google Patents

Control processing system

Info

Publication number
JPS5812051A
JPS5812051A JP56110428A JP11042881A JPS5812051A JP S5812051 A JPS5812051 A JP S5812051A JP 56110428 A JP56110428 A JP 56110428A JP 11042881 A JP11042881 A JP 11042881A JP S5812051 A JPS5812051 A JP S5812051A
Authority
JP
Japan
Prior art keywords
control
priority
occupancy
circuit
control table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56110428A
Other languages
Japanese (ja)
Inventor
Satoshi Kuroda
聡 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56110428A priority Critical patent/JPS5812051A/en
Publication of JPS5812051A publication Critical patent/JPS5812051A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To eliminate a failure of one control table from affecting on the other control table, by connecting an occupancy request line and an occpancy permission line to a common priority circuit through a microprocessor respectively provided to a plurality of control tables. CONSTITUTION:A microprocessor MPU is built in control tables 21-2n and they are connected to a device to be controlled 1 via a data bus 6 with the MPU for the giving/receiving of data. Each control table is connected to the priority circuit 5 with occpancy request lines 71-7n and occupancy permission lines 81-8n mutually. The circuit 5 discriminates the priority with the occupancy request signal from each MPU through the use of the software for the interlocking of operation information and when the device 1 is occupied with a specific control table for a prescribed time or more, an alarm is generated. The MPUs are decentrarizingly located for each control table and the interlocking is constituted witb the software, allowing to avoid a failure of a control table from being affected on the other control tables.

Description

【発明の詳細な説明】 本発明は、制御処理方式、特に複数の制御卓によって1
つの被制御装置を制御する場合の制御処理方式に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a control processing method, in particular, a control processing system that uses a plurality of control consoles to
This invention relates to a control processing method when controlling two controlled devices.

従来、IN数台の制御車によって1つの禎制御装鎗を制
御しようとする場合は第1図々示構成が採用されていた
Conventionally, when one control device is to be controlled by several control vehicles, the configuration shown in FIG. 1 has been adopted.

儂制御i1;f11114m対してl[数台の制御卓2
1〜2nがあり、前記各制御台から優先インターロック
回路3會介して各操作信号41〜4nと制−データが送
られる。そして優先インターロック回路3内にあるコン
トロール回路31では操作4Ii号4l−4nによって
優先順位が判定され、優先順位の高い制御データから順
次ゲート321〜321&をあけて被制御装置1にデー
タ上液していた。
I control i1; for f11114m l [several control consoles 2
1 to 2n, and each operation signal 41 to 4n and control data are sent from each control console via a priority interlock circuit 3. Then, in the control circuit 31 in the priority interlock circuit 3, the priority is determined by operations 4Ii 4l-4n, and the gates 321 to 321& are opened in order from the control data with the highest priority to transfer the data to the controlled device 1. was.

一方、操作員が、例えば制御卓21を操作するC;際し
て、被制御装置lがすでに制御卓2!l Cよって占有
されていると、制御卓21には他車C;よって使用中で
ある旨の表示がなされ、前記使用中の制御卓2nが占有
を解除するまで待九されるのが普通であった。
On the other hand, when the operator operates, for example, the control console 21, the controlled device l is already on the control console 2! If the control console 21 is occupied by another vehicle C, a message indicating that it is being used by another vehicle C is displayed on the control console 21, and a wait is normally made until the control console 2n currently in use releases the occupation. there were.

しかも通常インター−ツタ回路は複雑な回路構成を有し
、かつ多くの部品1;よって構成されて−る九め、故障
発生の確率も高く、1度インタ−ツク・コントロール回
路31が不要C;なると、各制御卓21〜2mからの制
御不能口陥りシステム停止になり得ること、及び操作員
6;とっては、いくら待っても制御できないことのみで
インターロック回路の不曳を予欄するのが困難であった
Moreover, the inter-interconnect circuit usually has a complicated circuit configuration and consists of many parts, so the probability of failure is high, and the inter-interconnect control circuit 31 is unnecessary. If this happens, the control consoles 21 to 2m may become uncontrollable, causing the system to stop, and Operator 6: No matter how long he waits, he will not be able to control the interlock circuit. was difficult.

本発明は上記問題点を解決することを目的としてなされ
たものであり、共通1;もうけられ九インターロック錦
路を各制御卓*(’:分散配置し、インターロック回路
tソ7トクエアC二よって構成することざ;より部品故
障の確率を少なくし、1つの制御車C二故障があっても
他の制御卓(:影響を与えないようC;すると共C;、
一定期間以上にわたって占有状態が継続した場合に、警
報を出し異常を知らせることのできる制御処理方式を提
供することを目的としている。
The present invention has been made with the aim of solving the above-mentioned problems, and common 1:9 interlock circuits are distributed on each control console *(': interlock circuit tso7txair C2). Therefore, the structure is designed to reduce the probability of component failure, so that even if one control vehicle fails, it will not affect the other control consoles.
It is an object of the present invention to provide a control processing method that can issue an alarm and notify an abnormality when an occupied state continues for a certain period of time or more.

以下図mを参照しつつ実施例を説明する。第2図は本発
W14ζ二よる制御処理方式の一実施例概略構成図、I
N3図は優先回路の一実施例構成図、第4図は各制御卓
C:おけるインターロック管フローチャートで示した図
、第5図は優先回路の他の実施例構成図である。
An embodiment will be described below with reference to FIG. FIG. 2 is a schematic configuration diagram of an embodiment of the control processing method based on the present invention W14ζ2, I
Figure N3 is a configuration diagram of one embodiment of the priority circuit, FIG. 4 is a diagram showing a flowchart of an interlock tube in each control console C:, and FIG. 5 is a configuration diagram of another embodiment of the priority circuit.

第2図C;おいて、符号1.21〜2nは第1図に対応
している。そして各制御卓21〜2nt:は夫々コンビ
エータが図示の如く組込まれ、!イクロプロセッf11
置(MPU )により、データバス6を介して皺制御鋳
置lC−豪続され、データのやりとりが行なわれ為、S
は優先1路であって、各制御車との間は占有リクエスト
J171〜7nと占有アクノリッジ線81〜8nと6:
よって相互C;接続がなされている。
In FIG. 2C, symbols 1.21 to 2n correspond to those in FIG. Each of the control consoles 21 to 2nt: has a combiator incorporated therein as shown in the figure. icroprocessor f11
The wrinkle control casting unit (MPU) is connected to the wrinkle control casting IC via the data bus 6, and data is exchanged.
is priority 1 road, and the lines between each controlled vehicle are occupancy requests J171-7n, occupancy acknowledge lines 81-8n and 6:
Therefore, a mutual connection is established.

第3図−よって優先回路を説明する。1lN3図書=お
いて、符号21〜gn p 5 e 7”〜7n及び8
1〜8nは第2図(二対応しそいる。511〜5111
は各制御卓にもうけられたIJ L/−であって、これ
が励磁されると接点531〜53m 、 561〜56
nを閉路し、接点541〜54nを開路する。同じり5
21〜52nは各制御卓l:もうけられたリレーであっ
て、これが励磁されると、接点551〜55m及び57
1−57nを夫々閉路する。そして本実施例の場合、制
御車21〜2nの順で優先が組まれている。即ち、最優
先順位にある制御卓21の占有リクエスト線71(:よ
ってリレー511を励磁すると、接点531が閉路して
電源が接続されると共3;、接点541を開路し、それ
以降にある優先順位の低い制御卓の回路は線断される。
FIG. 3 - The priority circuit will therefore be explained. 1lN3 books = 21~gn p 5 e 7''~7n and 8
1 to 8n correspond to Fig. 2.511 to 5111
is an IJ L/- provided on each control console, and when this is energized, contacts 531-53m, 561-56
n is closed, and contacts 541 to 54n are opened. Same 5
21 to 52n are relays installed on each control console, and when this is energized, contacts 551 to 55m and 57
1-57n are respectively closed. In the case of this embodiment, priority is set in the order of control vehicles 21 to 2n. That is, when the relay 511 is energized, the occupancy request line 71 of the control console 21 which has the highest priority, the contact 531 is closed and the power is connected, and the contact 541 is opened and the subsequent The circuits of the lower priority control consoles are disconnected.

そしてリレー521が励磁されると前記リレー521に
連動して接点571が閉となり、占有アクノリッジ線8
1(−よって占有許可が制御卓21C:与えられる。
When the relay 521 is energized, the contact 571 is closed in conjunction with the relay 521, and the occupancy acknowledge line 8
1 (- Therefore, occupancy permission is granted to the control console 21C.

なお制御卓21が被制御装置lを占有する(−際しては
、リレー521の励磁状態を調べることC二より、優先
順位の下位の制御卓2nがすで【;占有しているかどう
かをチェックする。
Note that if the control console 21 occupies the controlled device l (-, check the excitation state of the relay 521 from C2 to see if the control console 2n, which is lower in priority, is already occupying the controlled device l). To check.

上記占有許可が与えられるとデータ処理が開始されるが
、処理終了後はリレー511を消磁することC;より元
の状態へ後場される。
When the above-mentioned occupancy permission is granted, data processing is started, but after the processing is completed, the relay 511 is demagnetized and returned to its original state.

この場合、接点s41が閉路するため優先順位の下位の
制御卓の動作が可能となる。即ち、制御卓21が占有中
ζ;制御卓2n&:よって占有されることはない。
In this case, since the contact s41 is closed, the operation of the lower priority control console becomes possible. That is, the control console 21 is occupied ζ;control console 2n&: Therefore, it will not be occupied.

制御車21と211とが優先回路51一対して同時に占
有要求を出し九場合には、各リレー511 、51m 
When the control vehicles 21 and 211 simultaneously issue occupancy requests to a pair of priority circuits 51, each relay 511, 51m
.

521 、52mの動作タイζングC二よって制御卓2
1と2nとが同時C二占有されることを防ぐ九め、第4
図のフ四−チヤードで示すようCニ一旦占有要求確認後
、ある時間r−おいてもう一度、占有要求受付の確gを
とるようなされている。即ち、フローチャートにおいて
、一旦両者の占有要求を受付け、一定遅延時間後口受付
は再チェックをすることにより、優先順位を明らかにし
て後、優先順位の高い制御卓に対してのみ処m*行させ
るようζ;なされている。
521, 52m operation timing C2, control console 2
9th and 4th to prevent 1 and 2n from being occupied simultaneously by C2
As shown by the chart on the left in the figure, after confirming the occupancy request at C, confirmation of acceptance of the occupancy request is made again after a certain period of time r. That is, in the flowchart, once the occupancy requests from both parties are accepted, and after a certain delay time, the reception is rechecked to clarify the priority order, and then only the control console with the higher priority is processed. It has been done.

次C:アラーム出力6;ついて説明する。@3図々示(
:なる嗜隈タイマー91.hはオンディレィ・タイマー
であって、例えば制御卓雪nが占有すると接点55m及
び5G虱が共に閉となり時限タイマー9nを励磁する。
Next C: Alarm output 6; will be explained. @3 diagrams (
: Narufukuma Timer 91. h is an on-delay timer; for example, when the control table n is occupied, contacts 55m and 5G are both closed, and the timer 9n is excited.

し九がって設定時間が経過すると前記時限タイマー9a
は付勢され、外部にアラーム出力を導出する。そこで各
制御卓!1−2mは時限タイマー91.9mが動作する
以前6;被制御装置1の占有を完了するようにすれば、
制御卓の不jLxはリレー 51nの不良等により占有
の異常状態を検出することが可能となる。
Then, when the set time has elapsed, the timer 9a
is energized and outputs an alarm output to the outside. Each control console there! 1-2m is before the timer 91.9m operates 6; If the occupancy of the controlled device 1 is completed,
It becomes possible to detect an abnormal state of occupancy due to a failure of the relay 51n, etc. of the control console.

又、制御車3nの電源が喪失し九場合1;は、リレー5
1nを励磁する電流は制御卓2塁から供給されているた
め、前記リレー51aは励磁されず、これは占有要求食
出していない状態と同じC:なって他車−二影響を及ぼ
す仁とはない。
In addition, in case 1; when the power of control vehicle 3n is lost, relay 5
Since the current that excites 1n is supplied from the second base of the control console, the relay 51a is not energized, and this is the same state as when no occupancy request is issued. do not have.

第5図は優先回路の他の実施例である。そして本実施例
では制御卓ト1;ついてのみ示されており、他の制御卓
a;ついても同様構成をとるもので魯る。aa中の符考
21 、511 、 t21 、531 、541 、
551 。
FIG. 5 shows another embodiment of the priority circuit. In this embodiment, only the control console 1 is shown, and the other control consoles 1A and 1A are also of similar construction. References 21, 511, t21, 531, 541 in aa,
551.

SIX 、 871 I會l、は夫々第3図に対応する
ものであるが、本実施例r−シいては第3図々示リレー
521と前記リレーC;応動する接点551 、571
との関係をフォト宵プラ(;置きかえたtのである。
SIX, 871 I, respectively, correspond to FIG. 3, but in this embodiment, the relay 521 shown in FIG. 3 and the relay C; responsive contacts 551, 571
The relationship with the photo night pla (; has been replaced with t.

以上説明した如く、本発明によれば共通C二もうけられ
たインターロック回路を各制御卓C;夫々分散配置し、
ソフトウェアC;よってインターロックが構成されるの
で、部品の劣化に゛よるインターロック不実が1止され
ることは勿論のこと、電源喪失等ε:より制御卓が操作
不良となっても他の卓に何ら影響を及ぼすことなく、l
!t:時限タイマー(−
As explained above, according to the present invention, the interlock circuit provided in common C2 is distributed and arranged in each control console C;
Software C: Therefore, since an interlock is configured, it goes without saying that false interlocks due to deterioration of parts can be stopped, and even if the control console malfunctions due to power loss etc., other consoles can be l without any influence on
! t: Timed timer (-

【図面の簡単な説明】[Brief explanation of the drawing]

第XI!IIは従来方式鑑;よる複数の制御卓が被制御
装置を111#する制御方法を示し死因、第2図は本尭
1mによる制御II&量方式を示す一実施例構成図、m
s園は優先回路の一実施例構成図、11g4図は各制御
車r−ンけるインターロックを7酵−チャードで示し死
因、li’bs図は優先回路の傭の実施例構成図である
。 1−m−被制御装置、     2l−2n−−一制御
卓、3−m−優先インターロック回路、41〜軸−m−
操作信号、321〜32m−−−ゲート、   31−
−−コントルール回路、5−m−優先回路、     
 6−−−データ・パス、71〜7m−−一占有要求線
、   81〜811−−一占有許可線、鵡人軸土石井
紀男 馬2図 帛4図
Chapter XI! II shows a control method in which a plurality of control consoles control a controlled device according to the conventional method; FIG.
Figure 11g4 shows the configuration of one embodiment of the priority circuit, Figure 11g4 shows the interlock for each controlled vehicle in seven diagrams, and Figure 11g4 shows the configuration of an embodiment of the priority circuit. 1-m-controlled device, 2l-2n--control console, 3-m-priority interlock circuit, 41-axis-m-
Operation signal, 321~32m---Gate, 31-
--control circuit, 5-m-priority circuit,
6--Data path, 71-7m--1 occupancy request line, 81-811--1 occupancy permission line, 2nd map of Unin axis, 2nd map, 4th map.

Claims (1)

【特許請求の範囲】[Claims] (1)共通にもうけられ九被制御装置を複数の制御卓6
二よって優先順位にしたがい制御される制御処理方式(
;おいて、上記制御車C;は夫々!イク四プロセツti
装置をもうけ、各マイタ四プロセッサ舊;占有費求曽、
占有許可at通して優先回路1接続し、前記優先回路は
令マイクープロセッサ装置からの占有要求信号を受付は
ソフトウェアを用いて操作情報のインターロックが行な
われることt特徴とすゐ制御処理方式。 (舞共通C−もうけられ九被制御装置を複数の制御卓に
よって優先順位(;シたがい制御される餉御拓環方式口
お−で、上記制御卓C;は夫々!イクープロ竜ツナ装置
をもうけ、各マイクロブ四セツナζ;占有畳求−1占有
許可alt通してタイマー回路と警報装置とを有する優
先回路を接続し、前記優先回路は各マイクロプロセッサ
装置からの占有要求信号を受付はソフトウェアを用いて
操作情報のインターロックが行なわれると共−二、特定
制御卓によって一定時間以上継続して被制御装置が占有
された場合に警報を発することを特徴とする制御処理方
式。
(1) Multiple control consoles (6) to control controlled devices (9) in common
2. Control processing method controlled according to priority order (
; and the above-mentioned control vehicle C; respectively! Iku four process setti
Each miter has four processors;
The control processing method is characterized in that the priority circuit 1 is connected through the occupancy permission, and the priority circuit receives an occupancy request signal from the command processor and interlocks the operation information using software. (Mai common C- Created 9 controlled devices with priority order by multiple control consoles (; In the control console method that is controlled by each other, each of the above control consoles C; creates an Ikupro dragon tuna device. A priority circuit having a timer circuit and an alarm device is connected through the occupancy request-1 occupancy permission alt, and the priority circuit receives occupancy request signals from each microprocessor device using software. 2. A control processing method characterized in that an alarm is issued when a controlled device is occupied by a specific control console for a certain period of time or more.
JP56110428A 1981-07-15 1981-07-15 Control processing system Pending JPS5812051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56110428A JPS5812051A (en) 1981-07-15 1981-07-15 Control processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56110428A JPS5812051A (en) 1981-07-15 1981-07-15 Control processing system

Publications (1)

Publication Number Publication Date
JPS5812051A true JPS5812051A (en) 1983-01-24

Family

ID=14535493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56110428A Pending JPS5812051A (en) 1981-07-15 1981-07-15 Control processing system

Country Status (1)

Country Link
JP (1) JPS5812051A (en)

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