JPH03238551A - Data transfer system between cpu - Google Patents

Abstract

PURPOSE:To confirm whether or not incoming and outgoing data between a master CPU and a slave CPU are correct and to verify whether or not a circuit is present by detecting a data error from whether or not data stored in an incoming and an outgoing data buffer array match each other. CONSTITUTION:The master CPU 2 of a master unit 1 and the outside of the outgoing data buffer array 8 of a slave unit 6 are connected by an external data bus DB1 and the outside of the incoming data buffer array 9 and an external data bus DB1 are connected by an external data bus DB2. Then when the stored outgoing data is fetched by the slave CPU 7, the outgoing data is stored as feedback data into the incoming data memory 9 at the same time and the data error is detected from whether the feedback data matches the outgoing data or not. Consequently, incoming/outgoing correct/error confirmation between the master CPU 2 and slave CPU 7 and the verification of whether or not there is the circuit present are enabled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transmission system between CPUs, and particularly to a CPU that transmits and receives data between a master CPU and a slave CPU.
This relates to a data transmission method between PUs.

[Prior Art] A conventional data transmission method between CPUs is executed between a master unit 11 and a slave unit 16 shown in FIG. Further, the master unit 11 is composed of a master CPU 12, and the slave unit 16 is composed of a slave CPU 17 and a buffer array 18.

The master CPU 12 of the master unit 11 connects to the buffer array 18 of the slave unit 16 and the external data bus DB3.
, read, write signal lines RD, WR, and A interrupt signal line AIS, and connect the buffer array 18 and slave CP.
Ul7 is connected to slave internal data bus 5DR3, slave read and slave write signal lines SRD and SWR, and 8 interrupt signal lines BIS.

When there is down data from the master CPU 12 of the master unit 11 configured as described above to the slave CPU 17 of the slave unit 16, the write signal WR and the external data bus DB
, and sends the downstream data to the buffer array 18. When the buffer array 18 receives the write signal WR, it sends out the slave cP0178B interrupt signal BIS.

After receiving the 8 interrupt signal BIS, the slave CPU 17 reads the downstream data latched in the buffer array 18 via the slave internal data bus SDB using the slave read signal SRD after the current real-time processing is finished, and uses the slave read signal SRD to read the downstream data latched in the buffer array 18 via the slave internal data bus SDB. Perform internal processing based on data.

When there is upstream data from the slave CPU 17 to the master CPU 12, or when response data to the above downlink data is returned as upstream data, the slave CPU1
7 sends the slave write signal SWR and the upstream data via the slave internal data bus 5DB3 to the buffer 7 array 18.

When the buffer array 18 receives the slave write signal swR, it sends the A interrupt signal AIS to the master CPtJ12, so that the mask CPU that received the A interrupt signal AIS
After completing the real-time processing being executed, I2 sends the read signal RD to the buffer array 18, and the buffer array 1
The upstream data latched at 8 is read via the external data bus DB, and internal processing is performed based on the upstream data.

[Problems to be Solved by the Invention] The data transmission method between CPUs with the above configuration is, for example, when transmitting downlink data from the master CPU 2 of the master unit 11 to the slave CPU 7 of the slave unit 16, the downlink data latched by the buffer array 18 is There is no loopback structure to verify the health of the data. Therefore, even if the data latched in the buffer array 18 is not normal, the downstream data is transferred to the slave CPU 17, and the master CPU 12 does not know that invalid downstream data has been transferred to the slave C: PU 17, resulting in an illegal element. There is. In addition, if multiple slave units can be installed, not all functional blocks are always installed in the multiple slave units 16, so in this case, whether or not there are slave units 16... The problem is that it cannot be confirmed.

[Object of the Invention] The present invention has been made in view of the above-mentioned difficulties.
The downlink and uplink data transmitted between the PU and the slave CPU are temporarily stored in the downlink and upper redata buffer arrays provided in the slave unit, and the data stored in the downlink and upper redata buffer arrays match. Master CPU and slave CPU by detecting data errors
It is an object of the present invention to provide a data transmission system between CPUs that can confirm the correctness of downlink and uplink data between CPUs and verify the presence or absence of a circuit.

[Means for Solving the Problems] The data transmission method between CPUs according to the present invention is such that when transmitting data from a master CPU to a slave CPU connected to a data bus, there is a method for transmitting data from the master CPU to the slave CPU on the slave CPU side. A downstream data memory for latching data from the slave CPU to the master CPU is provided, and an upstream data memory for latching data from the slave CPU to the master CPU is provided, and the downstream data sent from the master CPU via the data bus is stored in the downstream data memory. death,
When the accumulated downlink data is taken into the slave CPU, the downlink data is simultaneously stored in the uplink data memory as feedback data, and data errors are detected based on whether the feedback data matches the downlink data. It is a method.

[Embodiment] An embodiment of the data transmission system between CPUs according to the present invention will be described in detail below with reference to FIG.

The data transmission method between CPUs according to the present invention is a data transmission method executed between a master unit 1 and a slave unit 6 shown in FIG.
U2, a decoder 3, a negative input NAND circuit 4 forming a read select signal generation section, and a negative input NAND circuit 5 forming a write select signal generation section, and the slave unit 6 includes a slave CPU 7 and a lower redata buffer array. 8 and an upper redata buffer array 9.

The master CPU 2 and decoder 3 of the mask unit 1 use the request signal line RQL and the mask internal address bus MAB.
Connected with Further, one negative input of each of the negative input NAND circuits 4.5 is connected to the output side of the decoder 3, and the other negative input of each of the negative inputs is also connected to the read/write signal line WR of the CPU 2. Note that the memory request signal MREQ or the input/output signal l0RQ is transmitted and received on the request signal line RQL.

The slave CPU 7 of the slave unit 6 and the downstream data buffer array 8 have an output ready signal line OR.
, a clear signal line CLR, and an output enable signal line OE. Note that the inside of the lower redata buffer array 8 to which the output enable signal line OE is connected is a negative input.

In addition, the upper data storage array 9 and slave CPU 7
is connected to the slave internal data bus SDR□ by an input ready signal line IR, and the inside of the lower redata buffer array 8 is connected to the slave internal data bus 5DR2 by a slave internal data bus 5DB1.

Further, the outer NAND input of the lower redata buffer array 8 and the NAND output of the NAND circuit 5 of the NAND input of the master unit 1 are connected by a write select signal line WDS, and the outer NAND input of the upper redata buffer array 9 and the NAND Connect the negative output of the input NAND circuit 4 with the read select signal line "Stone 1".

In addition, the master CPU 2 of the master unit 1 and the outer side of the lower redata buffer array 8 of the slave unit 6 are connected by an external data bus DB1, and the upper redata buffer array 9
external data bus DB1 and external data bus DB2.
Connect with.

[Operation of the invention] In order to transmit down data from the master CPU 2 to the slave CPU 7 between the mask unit 1 and the slave unit 6 having the above configuration, the output of the request signal line RQL connected to the re-decoder 3 from the master CPU 2 is activated. Then, the address data of the slave CPU 7 is sent to the decoder 3 via the master internal address bus MAB. Decoder 3 decodes the address of slave CPU 7,
Based on the output of the decoder 3 and the write signal WR of the master CPU 2, a write select signal WDS is generated at the negative output of the NAND circuit 5 having a negative input. Also, in synchronization with this write select signal WDS, the master CPU 2 selects the external data bus D.
Sends down data on B1. External data bus DB□
The upper downstream data is latched by the lower redata buffer array 8 to which the write select signal WDS is input, and
The latched downstream data is transferred to the slave internal data bus SD.
B□, 5Send on DB2. Further, the output ready signal OR notifies the slave CPU 7 that the downstream data has been latched.

In addition, in order to verify the correctness of the downlink data latched in the lower redata buffer array 9 and to confirm the presence or absence of the slave unit 6, the master CPU 2 converts the output of the decoder 3 and the read signal RD of the master CPU 2 into a negative input NAND. Send to circuit 4.

Since the NAND circuit 4 sends a negative input read select signal RDS to the outside of the upper redata buffer array 9 from the output of the decoder 3 and the read signal RD, the read select signal RDS
The upper data buffer array 9 that received the data reads out the downstream data remaining on the slave internal data buses 5DB1 and 5DB2 onto the external data buses DB2 and DB1 as upper data buses for feedback, and the master CPU 2 reads the remaining data on the slave internal data buses 5DB1 and 5DB2 as upper data buses for feedback. If the upstream data read out during the process matches the downstream data, it is assumed that the downlink data transmission process has been completed and the process moves on to the next process. If the uplink data for feedback and the downlink data do not match, it means that the downlink data has changed due to a failure or there is no slave unit 6, so the downlink data is retransmitted after performing a predetermined failure recovery procedure. Execute. If the uplink data for feedback and the downlink data match by retransmission of the downlink data, the process moves to the next step.

If there is no slave unit 6, the read select signal RDS causes the read data buffer array 9 to
The upstream data for feedback read by PU2 is all "H" or "L", which is not used in the upstream data for normal feedback, so the slave unit 6... is registered as present at the initial setting. , and prohibits access from the master CPU 2 from the processing onward, thereby reducing redundant processing time due to invalid access.

When transmitting upstream data from the slave CPU 7 to the master CPU 2, the slave CPU 7 sends an input ready signal I indicating the empty state of the upper data bus array 9.
After confirming R, upstream data is sent onto slave internal data bus 5DB2 connected to upper redata buffer array 9.

The upper data buffer array 9 is connected to the slave internal pig bus 5.
Latch the upstream data existing on DB2 and send it to the master CP
Wait for read from U2. In addition, the upper redata buffer array 9 that has latched the upstream data receives an input ready signal I.
R is inverted and the slave CPU 7 is notified that the upstream data has been latched.

While performing each process, the master CPU 2 polls the plurality of slave CPUs 7 that it supervises.

If the upstream data read at this time matches the verification downstream data transferred from the slave CPU 7 immediately before, the downstream data is not treated as transfer data. In this case, the upstream data from the slave CPU 7 to the master CPU 2 is invalidated, and if they do not match, it is validated and internal processing is performed using the upstream data.

Also, at this time, the upper redata buffer array 9 sets the input ready signal IR to an empty state, and the slave C
The CPU 7 is informed of the buffer empty status, and if there is further upstream data from the slave CPU 7, the above procedure is continued again.

Note that address data is given to Heragu, and data processing is performed so that no matter what data the uplink data and downlink data are, they do not have the same value.

In the above embodiment, a data transfer method between a plurality of CPUs belonging to one system has been described, but a data transfer method between a plurality of systems may be used.

[Effects of the Invention] The inter-CPU data transmission system according to the present invention latches data from the master CPU to the slave CPU on the slave CPU side when transmitting data from the master CPU to the slave CPU connected to the data bus. and an upstream data memory that latches data from the slave CPU to the master CPU, and stores downstream data sent from the master CPU via the data bus in the downstream data memory,
When the accumulated downlink data is taken into the slave CPU, the downlink data is simultaneously stored in the uplink data memory as feedback data, and data errors are detected based on whether the feedback data matches the downlink data. Because it is a master CPU and slave C
This has the effect of confirming the correctness of downlink and uplink data between PUs and verifying the presence or absence of a circuit.

[Brief explanation of drawings]

1 is a block diagram of a master unit and a slave unit related to the data transmission system between CPUs according to the present invention, and FIG. 2 is a block diagram of a master unit and slave unit related to the conventional data transmission system between CPUs. l...Master unit 2...Master CPU 6...Slave unit 7...Slave CPU 8...Lower data buffer array ( Downstream data memory) 9... Upper redata buffer array (upstream data memory)

Claims (1)

[Claims] Master CPU to slave CPU connected to data bus
A downlink data memory for latching data from the master CPU to the slave CPU on the slave CPU side and the slave CPU when transmitting data from the master CPU to the slave CPU.
An upstream data memory is provided for latching data from the master CPU to the master CPU via the data bus.
The downlink data sent from the PU is accumulated in the downlink data memory, and the accumulated downlink data is sent to the slave CPU.
When the data is imported into the CPU, the downstream data is simultaneously stored in the upstream data memory as feedback data, and an error in the data is detected based on whether or not the feedback data matches the downstream data. Transmission method.