JP2000181736A - Fail safe collation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate a data collation part with hardware, to reduce the control burden of a CPU core, to effectively use the CPU core and to miniaturize a device. SOLUTION: DMA controllers 6 and 11 which directly access RAM 5 and 10 without the aid of CPU cores 3 and 8 in MCU 1 and 2, serial transmission parts 7 and 12 operating the DMA controllers 6 and 11 and reading/transmitting information preserved in RAM 5 and 10, a data collation part 14 executing collation whether data transmitted from the serial transmission part 7 and data transmitted from the serial transmission part 12 are matched or not and an amplification part 15 outputting the collation result of the data collation part 14 and amplifying the output are installed. A device executing the operation of the data collation part 14 with hardware, reducing control burden by the software of the CPU cores 3 and 8, effectively using the CPU cores 3 and 8, reducing the control burden of the data collation part 14 and having simple constitution is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fail-safe verification device for monitoring the operation of a one-chip microcomputer.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a block configuration of a conventional fail-safe verification apparatus. In FIG. 4, fail-safe verification devices include two-system A and B-system microcontroller units (hereinafter referred to as MCUs) 50 and 51.
And a central processing unit (hereinafter referred to as CPU) cores 52 and 55 and memories 53 and 5 connected to the buses.
4, 56 and 57. The memories are ROMs 53 and 56 that are read-only memories and RAMs 54 and 57 that are readable and writable memories. MCU50,5
The first CPU cores 52 and 55 operate according to a timing signal sent from a timing generator 58 provided outside the MCUs 50 and 51. The ROMs 53 and 56 are operated by instructions from the CPU cores 52 and 55, and the results are stored in buffer registers 59 and 60, which are external memories, for each module, and the comparison unit 61 is operated by a program written in the ROMs 53 and 56. I do.

[0003] Buffer registers 59 and 60 and a comparison unit 61
Is a data collating unit 70. Activation of the output program to the data collating unit 70 is performed by two MCs
Since there is a time difference between U50 and U51, and the output of the data collating unit 70 repeats coincidence or noncoincidence, if the data collating unit 70 is constituted by a general-purpose comparator, the output will be a pulse signal. The MCUs 50 and 51 can predict whether or not the original output matches or does not match from the start timing of the output program.
By reading the data at 51, an abnormality of the data collating unit 70 can be detected.

If the output from the data collating unit 70 is a pulse signal that matches, the pulse signal is amplified by an output amplifier 64 and a normal relay 66 that switches through an AC-coupled rectifier 65 is excited, thereby providing a system. Is displayed on a display unit (not shown). When the output of the data collating unit 70 is in an abnormal state in which the outputs do not match,
The program stops running and the system cannot continue to operate. As a result, the normal relay 66
Is de-energized, and the output from the system is cut off, thereby ensuring the safety of the device.

FIG. 5 is a timing chart for explaining an example of data collation in the configuration of FIG. FIG. 5A shows that the processes in the MCU 50 are processes 1 to 4, and the CPU core 52 is stopped after the process 4. FIG. 5B shows a state in which the CPU core 55 is stopped in the middle of the processing 4 in the processing in the MCU 51 similarly to FIG. 5A. FIG. 5C shows results stored in the A-system buffer register 59 as results 1 to 3. FIG. 5D shows the result of storage in the B-system buffer register 60 as in FIG. 5C, and the storage result 3a is shown in FIG.
This indicates that the result does not match the result of (C). FIG. 5E shows that the output of the comparison unit 61 becomes a match or a mismatch with the comparison output. In FIG. 5 (F), when the result of FIG. 5 (E) is coincident, the system is activated and the system is operated. However, when the result of FIG. 5 (E) is not coincident, the system is not excited and the system is not operated. As a result, the device is stopped to realize fail-safe.

[0006]

However, in the conventional fail-safe collating apparatus, the output to the data collating unit is performed by the program processing, so that the software processing for the system operation during the data collation is limited. There are issues to be addressed. Further, since the output signal is generated by the program operation, the configuration of the amplifier circuit becomes complicated and large, so that the cost occupied by the amplifier is increased and the size of the entire device cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and a first object of the present invention is to directly access a memory without using a CPU by operating a data collating unit while an internal memory of an MCU is operating. When operated by the DMA controller, the operation of the data collating unit is performed by hardware to reduce the control load on the CPU, thereby effectively utilizing the CPU and the fail-safe data having a simple configuration in which the control load on the data collating unit is reduced. A collation device is provided.

A second object of the present invention is to simplify data processing in a data collating unit, thereby simplifying processing in data collation, simplifying the configuration in processing after data collation, and It is an object of the present invention to provide a general-purpose fail-safe collation device that can be easily applied to devices such as an electronic interlocking device, an electronic terminal device, and an electronic level crossing control device as various railway signal information systems.

[0009]

According to a first aspect of the present invention, there is provided a fail-safe collating apparatus comprising: a first or a second CPU in a first and a second MCU; and a first or a second CPU bus-connected to the first or the second CPU. In a fail-safe collation device including a memory, without using the first or second CPU,
A first or second DMA controller for directly accessing the first or second memory; and the first and second DMA controllers
A first and a second for operating a controller to read data stored in the first or second memory and transmit the data;
A transmission unit; and a data collation unit for collating whether the data transmitted from the first transmission unit matches the data transmitted from the second transmission unit.

According to the first aspect of the present invention, the operation of the collating circuit during the operation of the internal memory of the MCU is operated by the DMA controller which directly accesses the memory without passing through the CPU, thereby reducing the control load on the CPU. In addition to this, the number of programs can be reduced, and the size of the device can be reduced by reducing the control load on the data collating unit and simplifying the data collating unit.

According to a second aspect of the present invention, the first and second MCUs include first and second CPU cores and first and second memories bus-connected to the first and second CPU cores. In the fail-safe collating apparatus, a first or second DMA controller that directly accesses a first or second work table, which is the first or second memory, without passing through the first or second CPU core; A first and a second transmitting unit that operates a 2DMA controller to read data based on information stored in the first or second work table and transmits the data; and a data transmitted from the first transmitting unit. A data collating unit for collating whether the data transmitted from the second transmitting unit matches, and outputting a collation result of the data collating unit, Characterized by comprising an amplification section for amplifying.

According to the second aspect of the present invention, the operation of the matching circuit while the internal memory of the MCU is operating is operated by the DMA controller which directly accesses the memory, and
The control burden on the U-core is reduced, and the control burden on the data collating unit is reduced to simplify the data collating unit, simplifying the configuration of the data collating unit and configuring the amplifier on the output side of the data collating unit. And the size of the apparatus can be reduced.

[0013] According to a third aspect of the present invention, a fail-safe collating apparatus includes first or second CPU cores in first and second MCUs, and first or second memory bus-connected to the first or second CPU cores. In the fail-safe collating apparatus, a first or second DMA controller that directly accesses a first or second work table, which is the first or second memory, without passing through the first or second CPU core; A first DMA controller for operating the 2DMA controller to read data based on the information stored in the first or second work table and serially transmit the data;
And a second serial transmission unit; a data collation unit for collating whether data transmitted from the first serial transmission unit and data serially transmitted from the second serial transmission unit match; Output the collation result of
An amplifier for amplifying the output and a relay for operating based on the output of the amplifier are provided.

According to the third aspect of the present invention, the operation of the collation circuit while the internal memory of the MCU is operating is operated by the DMA controller which directly accesses the memory, and
The control load on the U-core is reduced, and the control load on the data collating unit is reduced, so that the data collating unit has a simple configuration. Further, by simplifying the configuration of the data collating unit and simplifying the configuration of the amplifying unit on the output side of the data collating unit, the size of the apparatus can be reduced. Further, when there is a mismatch in the contents of the work table due to the output of the amplification unit, the operation is stopped to ensure the reliability of the operation of the device,
The safety of the device can be improved.

According to a fourth aspect of the present invention, there is provided the fail-safe collating apparatus according to the third aspect,
The data matching unit receives the data output from the MCU, outputs matched data from the data matching unit to the amplifying unit when the data matches, and outputs the matched data when the data does not match. The output of the amplifying unit is fixed by storing a mismatch state.

According to a fourth aspect of the present invention, each data output from the MCU is input, and when the data match, the matching data is output from the data collating unit to the amplifying unit. The mismatch state is stored in the data collating unit, and the output of the amplifying unit is fixed. Thus, when there is a mismatch in the contents of the work table due to the output of the amplifier, the safety of the device can be improved by fixing the output of the amplifier to stop the operation and ensuring the reliability of the operation of the device. it can.

According to a fifth aspect of the present invention, there is provided the fail-safe collating apparatus according to the third or fourth aspect, wherein the MCU includes a memory, a serial transmission unit, a parallel transmission unit, and a DMA controller. And

In the fail-safe collating device according to the fifth aspect, the MCU includes a memory, a serial transmission unit, a parallel transmission unit, and a DMA controller.

According to a sixth aspect of the present invention, there is provided a fail-safe matching apparatus according to the fifth aspect,
The serial transmission unit or the parallel transmission unit is characterized in that a single clock generation unit is externally connected to give the same timing.

In the fail-safe collating device according to the sixth aspect, the serial transmission unit and the parallel transmission unit are built in the MCU by connecting a single clock generation unit to the outside in order to give the same timing. Make effective use and economical.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a fail-safe collating device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration of a fail-safe collation device according to an embodiment of the present invention. The two systems A and B include first and second MCUs (microcontroller units) 1, 2
Place. The MCUs 1 and 2 are, for example, one-chip microprocessors used for communication equipment for operation security and communication equipment for passenger business. MCU1 and MCU2 are the first and second C
PU (Central Processing Unit) cores 3, 8,
As a first and a second memory via a bus line
M4, 9, RAMs 5, 10, first and second DMA (direct memory access) controllers 6, 11, and first and second serial transmission units 7, 12, respectively. The I / Os 18 and 19 are connected to an external interface according to instructions from the CPU cores 3 and 8.

The DMA controllers 6 and 11 directly access the RAMs 5 and 10 without passing through the CPU cores 3 and 8. The serial transmission units 7 and 12 are provided with the DMA controllers 6 and
11 is operated to read data based on the information stored in the RAMs 5 and 10, and transmit the data serially.

The serial transmission units 7 and 12 perform serial transmission based on a clock generation signal output from the clock generation unit 13. The data matching unit 14 checks whether or not the data transmitted from the serial transmission unit 7 matches the data transmitted from the serial transmission unit 12.

The amplifying unit 15 outputs the result of collation by the data collating unit 14 and amplifies the output. AC-coupled rectifier 1
6 rectifies the output of the amplifier 15. The normal relay of the relay unit 17 operates based on the output of the rectifier 16.

The above-described apparatus directly controls the operation of the data collating unit 14 while the internal memories 4 and 5 or the internal memories 9 and 10 of the MCUs 1 and 2 are operating without passing through the CPU cores 3 and 8. The data is DMA-transferred to the serial transmission units 7 and 12 by the DMA controllers 6 and 11 which access the data as indicated by the chain lines. As a result, the control burden on the CPU cores 3 and 8 is reduced, and the data collating unit 1
4 to reduce the control load and simplify the data collating unit 14. In addition, the amplification unit 15 on the output side of the data collation unit 14
By simplifying the configuration, the size of the apparatus can be reduced. Further, when there is a mismatch in the contents of the work table due to the output of the amplification unit, the safety of the device can be improved by stopping the operation and ensuring the safety of the operation of the device.

FIG. 2 is a diagram showing a D which is a main part of an embodiment of the present invention.
FIG. 3 is a diagram illustrating MA transfer. In the description of FIG.
Referring to the block diagram of FIG. The RAMs 5 and 10 are composed of work tables 20 and 21, and the DMA controllers 6 and 1
Data is written for each slot of the work tables 20 and 21 by a control signal from the control table 1. Work table 20,
The data written in each of the slots 21 is read out by read signals from the DMA controllers 6 and 11, and transmitted to the serial transmission units 7 and 12 as shown by chain lines. Thus, when there is a mismatch between the contents of the work tables 20 and 21 due to the output of the amplification unit 15, the operation is stopped to prevent the device from failing, thereby realizing fail-safe.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a timing chart for explaining a data collating operation in the fail-safe collating device. FIG. 3A shows A-system bus data.
DM between the operation of the U core and the operation of the CPU core
There is time to operate the A controller. FIG. 3B shows B-system bus data, in which the operation timings of the DMA controller are provided similarly to FIG. 3A.

FIG. 3C shows a clock signal generated by the clock generator 13. FIG. 3D shows a serial output transmitted from the serial transmission section 7 in synchronization with the timing of FIG. 3C, and FIG. 3E shows an output from the serial transmission section 12 as in FIG. Serial output
Unlike the serial 3 shown in FIG. 3D, a part of the serial output shown in FIG.

FIG. 3 (F) shows the collation output of the data collation unit 14, but shows a state where the data is output only halfway due to a mismatch in the serial 3. In this case, the data in the disagreement state is stored in the data matching unit 14. FIG. 3 (G) shows that the data collating unit 14 operates the system by energizing the relay when it is determined that they match, and does not operate the system by energizing the relay when it is determined that they do not match. . This realizes fail-safe of the device. In FIG. 3 (G), it takes a long time to go from the high level indicating the excitation of the relay to the low level state due to the time constant of the rectifier 16 of the AC coupling between the amplifying unit 15 and the relay unit 17. Because of the delay.

In the above-described embodiment, the serial transmission units 7 and 12 are exemplified as the data transmission unit. However, the present invention is not limited to this, and a parallel transmission unit (not shown) may be used. In this case, parallel transmission becomes possible. Thereby, the parallel interface built in the one-chip microcomputer can be effectively used.

[0031]

As described in detail above, the present invention provides an MCU
The operation of the data collating unit is performed by hardware by operating the DMA controller which directly accesses the memory without the intervention of the CPU, and the operation of the data collating unit is performed by hardware of the CPU core while the internal memory is operating. The control load can be reduced and the CPU core can be effectively used, and the control load of the data collating unit can be reduced to provide a device having a simple configuration.

According to the present invention, the size of the apparatus can be reduced by simplifying the configuration of the amplifier on the output side of the data collating unit, and the contents of the work table can be reduced by the output of the amplifier. When there is a mismatch, the safety of the device can be improved by stopping the operation and ensuring the safety of the operation of the device.

Further, according to the present invention, when the data output from the serial transmission unit incorporated in the MCU is judged by the data collation unit to be coincident, the coincidence data is sent from the data collation unit to the amplification unit. Output, and when the data does not match, by storing the mismatch state of the data in the data matching unit and fixing the output of the amplification unit, when there is a mismatch in the contents of the work table due to the output of the amplification unit,
In order to stop the operation, the output of the amplifier is fixed and the apparatus is stopped beforehand, so that fail-safe of the apparatus can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a main part in FIG. 1;

FIG. 3 is a timing chart illustrating the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional configuration.

FIG. 5 is a timing chart illustrating an operation in the configuration of FIG. 4;

[Explanation of symbols]

1,2 ... first or second MCU (microcontroller unit), 3,8 ... first or second CPU (central processing unit) core, 4,9 ... ROM, 5,
10 first or second memory (RAM), 6, 11 first or second DMA (direct memory access) controller, 7, 12 first or second serial transmission unit,
13 clock generator, 14 data collating unit, 15 amplifying unit, 17 relay unit, 20, 21 work table.

Claims (6)

[Claims] The first or second MCU in the first and second MCUs.
In a fail-safe collation device including a CPU and a first or second memory bus-connected to the first or second CPU, the first or second memory is directly accessed without passing through the first or second CPU. A first or second DMA controller; first and second transmission units that operate the first and second DMA controllers to read data stored in the first or second memory and transmit the data; and the first transmission. A fail-safe collating device comprising: a data collating unit for collating whether the data transmitted from the unit and the data transmitted from the second transmitting unit match. 2. The first or second MCU in the first and second MCUs.
A fail-safe collation device including a CPU core and first and second memories bus-connected to the first or second CPU core, wherein the first or second memory is not interposed through the first or second CPU core. A first or second DMA controller for directly accessing a first or second work table, and operating the first and second DMA controllers to transfer data based on information stored in the first or second work table. First and second transmission units for transmitting read data; a data collation unit for collating whether data transmitted from the first transmission unit matches data transmitted from the second transmission unit; A fail-safe collating device comprising: an amplifying unit that outputs a collation result of the data collating unit and amplifies the output. 3. The first or second MCU in the first and second MCUs.
A fail-safe collation device including a CPU core and a first or second memory bus-connected to the first or second CPU core, wherein the first or second memory is not interposed through the first or second CPU core. A first or second DMA controller for directly accessing a first or second work table, and operating the first and second DMA controllers to transfer data based on information stored in the first or second work table. First and second serial transmission of read data
A serial transmission unit; a data collation unit for collating whether data transmitted from the first serial transmission unit and data serially transmitted from the second serial transmission unit match; and collation of the data collation unit. A fail-safe verification device comprising: an amplification unit that outputs a result and amplifies the output; and a relay unit that operates based on an output of the amplification unit. 4. The data collating unit inputs data output from the MCU, and when the data matches,
4. The failure according to claim 3, wherein the matching section outputs matched data to the amplifying section, and when the data does not match, stores the mismatch state of the data and fixes the output of the amplifying section. Safe collation device. 5. The fail-safe verification device according to claim 3, wherein the MCU includes a memory, a serial transmission unit, a parallel transmission unit, and a DMA controller. 6. The fail-safe verification device according to claim 5, wherein the serial transmission unit or the parallel transmission unit is connected to an external clock generation unit to provide the same timing.