JPS58120311A - Limiter - Google Patents

Abstract

PURPOSE:To obtain a limiter circuit of high performance with a simple constitution, by supplying a bias power supply to the base of one of a differential pair of transistors and at the same time connecting an output terminal and a level limiting transistor to the base of the other transistor respectively. CONSTITUTION:An end of a resistance R11 is connected to an input terminal, and the other end is connected to an output terminal, the base of a transistor TRQ1 and the collector of a TRQ5 of opposite polarity. A TRQ2 having a bias power supply VB connected to the base forms a differential pair with the TRQ1. The emitters of the TRQ1 and Q2 are connected in common and then connected to a power supply VCC via a constant current source I1. The base of the TRQ5 is connected to the collector of the TRQ2, and the collectors of the TRQ1 and Q2 are connected to a negative power supply via a current mirror pair of TRQ3 and Q4. When the level of an output terminal OUT rises up to the value approximately equal to the voltage VB, the TRQ1 becomes nonconductive and the TRQ2 starts its conduction. When the current of the TRQ2 exceeds that of a TRQ4, this differential flows to the base of the TRQ5. Then the collector current of the TRQ5 flows, and the voltage drop of an R11 is increased and then becomes steady when the base potential of the TRQ1 is equal to the voltage VB. Thus the output voltage is kept at a constant level.

Description

[Detailed description of the invention] (Technical field of invention) The present invention relates to a slider suitable for electronic circuits in general.

(Technical Background of the Invention and its Problems) Conventionally, in various electronic circuits, the purpose of limiting the signal (DC) level t so that it does not go above or below a certain arbitrary value (including 0) has been , j II A limiter as shown in Figures (I) and (b) is used. In other words, (1) is a resistance Rm between the input and output terminals IN and OUT.
This is a circuit in which a series circuit of a bias power supply ym with the polarity shown and a diode DI is connected in parallel through k, and as shown by the solid line in Diagram 2, approximately VF + V
B (where Vv is the diode DIe) I [direction voltage] which can be limited to a level.

In addition, in (b), an operational amplifier OF and a diode Dl are connected in a bypass manner between the input and output terminals IN and OUT via a resistor Rat, and a bias power supply Vl is connected to the other input terminal of the operational amplifier OF. It is a circuit like that, and the second
As shown by the broken line in the figure, it can be limited to a level of Vm.

However, while (a) has a simple configuration, it has the disadvantage of poor performance, and (b) has high performance but has the disadvantage of having an overly complex configuration. It had its pros and cons.

(Objective of the Invention) Therefore, this invention has been made in consideration of the above points, and one object is to provide an extremely nut-loving electric ivy that has been modified to have a relatively simple structure and high performance. 0 (Summary of the Invention) In other words, the Rintsuta according to the present invention includes a resistor having one end connected to the input end and the other end connected to the output end, one base connected to the output end, and the other base connected to the bias. A differential pair transistor is connected to the power supply and a common emitter is connected to a constant current source for detecting the next input level. is characterized in that the base is connected to the collector of the other, and a transistor for limiting nine levels is provided.

(Embodiment of the Invention) An embodiment of the invention will be described below in detail with reference to the drawings. That is, as shown in FIG. Output terminal OUT via
and the base of transistor Q1.

Here, the transistor Q1 has a bias power supply vm at its base.
is connected to the transistor Q.

0 and this differential pair transistors Q1-Qt are formed into a differential pair with their common emitters connected to a constant current source I
A pair of transistors Qs=Qat are connected to the positive power supply +Vcc K through I, and their respective collectors are connected to the
It is connected to the negative power supply -vH via the negative power supply -vH.

It, a level limiting transistor Q whose collector is connected to the QIC base of the differential pair transistors Q1-Ql and whose base is connected to the collector of the same <QX, has its emitter connected to the negative power supply -Vll.

In the above configuration, the input signal applied from the input terminal IN, that is, from the output terminal OUT, JTI! When the level of the output signal applied to i is lower than the bias power supply Vl voltage, the differential pair transistor Q*-Qm has Ql conductive and Q
, becomes non-conductive.

As a result, in such a state, the current pair of transistors Ql=Q4 is conductive and the level limiting transistor Qs is non-conductive, so that the input signal is applied to the resistor Ru'?
It is led out to the output terminal OUT through the terminal.

Next, suppose that the level of the input signal (that is, the output signal) rises to 11 degrees, which is the same as the bias power supply Vl voltage. The differential pair transistor QtsQ weight is such that the conduction of QS becomes non-conductive and the non-conduction of Qt begins to become conductive.As a result, the current of %Ql becomes the current of the pair of transistors Ql=Q4. When the current becomes larger than the current on the input side Q4, the difference current flows to the base of the level limiting transistor Qs, so the wrinkle Q
wK collector current will begin to flow.

Then, the potential drop across the resistor R11 increases, and stability is maintained in a state in which the base potential of Q1 of the differential pair transistors Q1-Q1 becomes approximately equal to the base potential of Q1, that is, the bias power supply voltage V.sub.1.

In this case, the maximum current of the level limiting transistor Q@ is the one given when QS of the differential pair transistor Qx-Q is non-conductive and Ql is conductive, and it is the DC current of When the current amplification factor is 1/!・! (However, l is the current of constant current ill) 0 In other words, the maximum potential drop across resistor R11 is!・■・RII
The limiter operable maximum input vt (Reimu X) is given by Vt (mAx) = Vl + / Bow * RH.

FIG. 4 shows a general value of Vl t = IV.

R,,-10 is #, l-10, /=100, that is, the maximum lint current is /"I=1am, and the maximum clearance input voltage Vf (Iris x) = Vl+/...!-hat, -11V
This shows the input/output transfer characteristics when the time is 9. According to this, the output potential fluctuation from the start of the limiter operation noise until the end of the tsuta operation is suppressed to about 100mVO range of about 1.1V. Therefore, it can be seen that high-performance glue can be achieved with a relatively simple configuration.

It goes without saying that this invention is not limited to the embodiment O described above and illustrated, and that various modifications and applications can be made without departing from the gist of the invention.

For example, a resistor or a diode may be inserted into the differential pair transistors QI-QtO to widen the range of output level fluctuation during the differential operation.

In addition, the current pair of transistors QseQ4 is not necessarily used, and other loads such as resistors or constant current sources may be used in place of Q4.Then, the level-limiting transistor Qsk Darlington connection is used. By doing so, the operable width of the rinsing device may be expanded by a factor of the composite current amplification factor.

Furthermore, as shown in FIG. 5, by connecting the current output transistor Q@ with the same characteristics whose pace is directly connected to the pace of the level limiting transistor Q in FIG. (However, N can be suppressed to the emitter area ratio of Qs-Q.) so as not to be affected by the β fluctuation.

In the case of Fig. 5, the collector current of the transistor QlO is approximately proportional to the input signal, so Fig. 6-)
It becomes possible to use it as a half-wave rectifier circuit that can obtain the waveform relationships shown in , (b), and (e). That is, the rectified output current Ivy flowing to the collector of the transistor Q for the input voltage Vim as shown in (a) is (
, ) is the positive half number im 1. υ! Middle 1- (however, Vln is the input signal voltage)
and 1. in the negative half cycle. υt = Q. Note that the output voltage voot generated at the collector of the transistor Qs is as shown in (b) (opposite to 1out) Also, the polarity IpNp of all the transistors in FIG.
: If mutually converted as NpN, a negative voltage can be realized (a half-wave rectifier circuit with a waveform relationship of opposite polarity to that in the tsuta or jlEa diagram can be realized.) Figure 7 shows the combination of the above sides. aS diagram by)
, (b), (e) The positive and negative limiter tX with the waveform relationship shown in IN is a double-wave rectifier circuit. (Effects of the Invention) Therefore, as detailed above, according to the present invention, it is possible to provide an extremely good connector that can achieve high performance with a relatively simple configuration.

[Brief explanation of the drawings] Figures 1 (1) and (b) are configuration diagrams showing conventional glue ζ vines. , FIG. 3 is a circuit configuration diagram showing an embodiment of the wooden ivy according to the present invention, and FIG. 4 is! FIG. 3 is a curve diagram illustrating the input/output transfer characteristic, and FIGS. 5 to 8 are diagrams showing circuit configuration diagrams and waveforms of each part according to other different embodiments. IN...Input terminal, R31...Resistor, OUT...i
end, Ql-Ql...differential pair transistor, Qs
m Q4...Pair of current transistors, ■...
- Constant current source, Q-... level limiting transistor. Applicant's agent Patent attorney Takehiko Suzue 1151 (a) (b) Figure 13 fs4 Figure Vl (M^X) Figure 5 1!611 Figure 1s8

Claims (1)

[Claims] A resistor having one end connected to an input end and the other end connected to an output end KII, one pace connected to the output end and the other pace connected to a bias power supply, and a common emitter connected to a constant current RII.
The differential pair transistors have opposite polarity and a level limiting transistor whose collector is connected to one of the transistors and whose collector is connected to the collector of the other. [Featured limiter.