JPS6033717A - Current mirror circuit - Google Patents

Current mirror circuit

Info

Publication number
JPS6033717A
JPS6033717A JP58142828A JP14282883A JPS6033717A JP S6033717 A JPS6033717 A JP S6033717A JP 58142828 A JP58142828 A JP 58142828A JP 14282883 A JP14282883 A JP 14282883A JP S6033717 A JPS6033717 A JP S6033717A
Authority
JP
Japan
Prior art keywords
current
transistor
collector
resistor
mirror circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58142828A
Other languages
Japanese (ja)
Other versions
JPH0151207B2 (en
Inventor
Atsushi Ogawa
敦 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58142828A priority Critical patent/JPS6033717A/en
Publication of JPS6033717A publication Critical patent/JPS6033717A/en
Publication of JPH0151207B2 publication Critical patent/JPH0151207B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To attain low voltage operation by connecting resistor between a base and a collector of a transistor (TR) being a component of a current mirror circuit and supplying an input current to the collector of the said TR. CONSTITUTION:When a current of an input current source IIN is 0, since a current IO flows to the 1st and 2nd TRs Q21, Q22, a voltage drop of R11.IO is produced across a resistor R11. Since a collector-emitter voltage VCE of the Q21 is VBE-R11.IO by the voltage drop, a VCE[Q21] is nearly 0.35V in setting the R11.IO to nearly 0.35V. In adding a current from the input current source IIN next, the operating current of the Q21 is IO+IIN. Further, a current flowing to the Q22 having the common base to the Q21 is also IO+IIN. Since the current flowing to the resistor R11 is IO and no change is caused by the input current IIN, the colector-emitter voltage VCE of the Q21 is constant and the VCE, i.e., the potential of a point A is lowered as low as possible.

Description

【発明の詳細な説明】 〔発明の技術分野〕 ミラー回路に係シ、特にその低電圧動作化を図ったもの
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to mirror circuits, and particularly to mirror circuits designed to operate at low voltages.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来、音響機器を含む電子機器一般に広く使用されるカ
レントミラー回路として第1図に示すように構成された
ものが知られている。
2. Description of the Related Art Conventionally, a current mirror circuit configured as shown in FIG. 1 is known as a current mirror circuit widely used in general electronic equipment including audio equipment.

すなわち、入力電流源IXNより入力電流がコレクタに
供給されるダイオード接続トランジスタQ1 とベース
を共通に接続したトランジスタQ2のコレクタから定電
流出力I。UTを得るようにしたものである。
That is, a constant current output I is output from the collector of a transistor Q2 whose base is commonly connected to a diode-connected transistor Q1 whose collector receives an input current from an input current source IXN. This is to obtain UT.

しかしながら、かかる第1図のカレントミラー回路は、
第2図に示すように、入力電圧のvINに接続された差
動接続トランジスタQs=Q<によシ駆動しようとした
場合、トランジスタQ1のベース・エミッタ間電圧VB
F、(約0.7V)が妨げとなって、トランジスタQ4
が飽和してしまうために、カレントミラー動作をなし得
ないという問題を有していた。
However, the current mirror circuit shown in FIG.
As shown in FIG. 2, if an attempt is made to drive the differentially connected transistor Qs connected to the input voltage vIN so that Qs=Q<, then the base-emitter voltage VB of the transistor Q1
F, (approximately 0.7V) becomes a hindrance, and the transistor Q4
The problem has been that the current mirror operation cannot be performed because the current is saturated.

とのため、第3図に示すようにエミッタを入力電流源I
□と抵抗R1との接続点に且つベースを定電流源工。と
ダイオードQttおよび抵抗1t2との接続点に接続し
たトランジスタQ12のコレクタから定電流出力■。U
Tを得るようにしたカレントミラー回路が考えられてイ
ル。
Therefore, as shown in Figure 3, the emitter is connected to the input current source I.
Install a constant current source at the connection point between □ and resistor R1 and at the base. Constant current output ■ from the collector of transistor Q12 connected to the connection point between diode Qtt and resistor 1t2. U
A current mirror circuit that obtains T is considered.

そして、かかる第3図のカレントミラー回路は、第4図
に示すように上記第2図のそれと同様な関係で駆動した
場合に、正常なカレントミラー動作をなすことができる
The current mirror circuit of FIG. 3 can perform normal current mirror operation when driven in the same relationship as that of FIG. 2 as shown in FIG. 4.

しかしながら、この場合抵抗R1,R,、VCよる電圧
降下がダイオードQllおよびトランジスタQ1□のV
□と直列になるため、電源■cc電圧が1v以下の如き
低電圧動作化を図ることが回器であるという問題を有し
ていた。
However, in this case, the voltage drop due to resistors R1, R, VC is
Since it is connected in series with □, there is a problem in that it is necessary to operate at a low voltage such that the cc voltage of the power supply □ is 1 V or less.

〔発明の目的〕[Purpose of the invention]

そこで、この発明は以上のような点に鑑みてなされたも
ので、可及的に簡易な構成で電源電圧がlv以下の如き
低電圧動作化を図ることが容易に可能となるように改良
した極めて良好なカレントミラー回路を提供することを
目的としている。
Therefore, this invention has been made in view of the above points, and has been improved so that it is easily possible to operate at a low voltage, such as when the power supply voltage is LV or less, with the simplest possible configuration. The purpose is to provide an extremely good current mirror circuit.

〔発明の概要〕[Summary of the invention]

すなわち、この発明によるカレントミラー回路は、各エ
ミッタが基準電位点または電源に接続されると共に各ペ
ースが互いに共通に接続された第1および第2のトラン
ジスタと、これら第1および第2のトランジスタの共通
ベースと電源または基準電位点間に接続された定電流源
と、前記i1のトランジスタのベース・コレクタ間に接
続された抵抗とを具備し、前記定電流源および抵抗とに
より前記第1のトランジスタのコレクタ電位をベース電
位よりも低く設定すると共に、前記第1のトランジスタ
のコレクタに入力端子を供給し、且つ前記第2のトラン
ジスタのコレクタから出力電流を導出するように構成し
たことを特徴としている。
That is, the current mirror circuit according to the present invention includes first and second transistors whose respective emitters are connected to a reference potential point or a power source and whose respective paces are commonly connected to each other, and of these first and second transistors. A constant current source connected between a common base and a power supply or a reference potential point, and a resistor connected between the base and collector of the transistor i1, and the constant current source and the resistor The transistor is characterized in that the collector potential of the transistor is set lower than the base potential, an input terminal is supplied to the collector of the first transistor, and an output current is derived from the collector of the second transistor. .

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の一実施例につき詳細に説
明する。
An embodiment of the present invention will be described in detail below with reference to the drawings.

すなわち、第5図に示すように第1のトランジスタQ2
1は、そのコレクタが入力電流源IINを介して電源v
ccに接続されると共に抵抗R11を介し′〔自らのベ
ースに接続され且つそのエミッタが基準電位点GNDに
接続されている。
That is, as shown in FIG.
1 has its collector connected to the power supply v via the input current source IIN.
cc, and is connected to its own base via a resistor R11, and its emitter is connected to the reference potential point GND.

また、第2のトランジスタQ22はそのペースが上記第
1のトランジスタQ21のペースに共通に接続されると
共に定電流源I。を介して電源vCCに接続され、且つ
そのエミッタが基準電位点GNDに接続され、さらにそ
のコレクタが定電流出カニ。UTを導出可能なようにな
されている。
Further, the second transistor Q22 has its pace commonly connected to the pace of the first transistor Q21, and is connected to the constant current source I. It is connected to the power supply vCC through the terminal, and its emitter is connected to the reference potential point GND, and its collector is a constant current output terminal. It is designed so that UT can be derived.

而して、以上の構成において、入力電流源’INからの
電流がOのときは、第1図に示したカレントミラー回路
と同様な動作tし、第1および第2のトランジスタQ2
1.Q2□にはInなる電流が流れるようになる〇 また、抵抗R11にも■B(=■o)なる電流が流れる
ようになるため、その両端にはR11・工。なる電圧降
下が生じる。
In the above configuration, when the current from the input current source 'IN is O, the operation is similar to that of the current mirror circuit shown in FIG. 1, and the first and second transistors Q2
1. A current In will now flow through Q2□. Also, a current ■B (=■o) will flow through the resistor R11, so R11 is connected to both ends of it. A voltage drop occurs.

これによって、第1のトランジスタQ21のコとなるの
で、■L11・Ioを0.35 V程度に設定してやれ
ばvCE(Q21)も0.35 V程度となる。
This makes it the same as the first transistor Q21, so if L11·Io is set to about 0.35 V, vCE (Q21) also becomes about 0.35 V.

次に、入力端子源IINからの電流が増大する方向に加
えられた場合には、第1のトランジスタQ21の動作電
流は1゜+’INとなる。
Next, when the current from the input terminal source IIN is applied in an increasing direction, the operating current of the first transistor Q21 becomes 1°+'IN.

また、上記第1のトランジスタQ21とペース共通の第
2のトランジスタQ22に流れる電流も(■o十工、N
)となる。
In addition, the current flowing through the second transistor Q22, which has a common pace with the first transistor Q21, also flows (
).

このとき、抵抗R11[流れる電流は工。であって、入
力電流源■INによる変化は生じない。
At this time, the resistor R11 [the flowing current is Therefore, no change occurs due to the input current source ■IN.

つまり、抵抗gx□の電圧降下は−だであシ、第1のト
ランジスタQ21のコレクタ・エミッタ間′亀圧vcF
!も一定となるもので、該vcIeずなわち図示(A)
点の電位を低くすることができるため、第6図に示すよ
うな適用が可能となる。
In other words, the voltage drop across the resistor gx□ is -, and the voltage drop between the collector and emitter of the first transistor Q21 is vcF.
! is also constant, and the vcIe, that is, as shown in (A)
Since the potential at a point can be lowered, applications as shown in FIG. 6 are possible.

すなわち、第6図は第5図の人力化ぢ号Hx工、を第3
および第4のトランジスタ(4□3#’J24でなる差
動回路に置き換えたもので、図中のvINは入力電圧源
、Iは定電流源である。
In other words, Figure 6 shows the human-powered No. 3 Hx machine in Figure 5.
and a fourth transistor (4□3#'J24), vIN in the figure is an input voltage source, and I is a constant current source.

エミッタ間電圧vCEを0.35 V程度とすることに
より、第4のトランジスタQ24はそのVC)i、が0
.3SViTff1度となって、飽和することなく正常
なカレントミラー動作をなすことができるようになる。
By setting the emitter voltage vCE to about 0.35 V, the fourth transistor Q24 has its VC)i, 0.
.. 3SViTff becomes 1 degree, and normal current mirror operation can be performed without saturation.

この場合、電源V。、:と基準電位点GND間には使用
するトランジスタのベース・エミッタ間電圧vBoとコ
レクタ・エミッタ間−圧VcE以外には直列につながら
ない如く電圧ロスが小さくなっておシ、voc〈0.8
vの如き可及的に低電圧動作化がuJ能となるものであ
る。
In this case, the power supply V. , : and the reference potential point GND, the voltage loss is small so that there is no series connection other than the base-emitter voltage vBo of the transistor used and the collector-emitter voltage VcE, voc<0.8
This makes it possible for uJ to operate at as low a voltage as possible.

そして、定電j4シ源■。の電流値をV。VC比例した
電流値として適切な値に設定するととQてより、第1の
トランジスタQ2□のvc、を温度変化によらず、常に
7VBF、とすることができる・第7図は他の実施例と
して第5図のトランジスタの極性を入れ換えた場合を示
している。そして、ベース電流の影響を小さくするだめ
の補償母抗It 、□が挿入されていると共に、エミツ
タ面績を大きくして電流利得をとるだめの出力用トラン
ジスタQC5が挿入されている。
And constant voltage j4 source■. The current value is V. By setting the current value proportional to VC to an appropriate value, the VC of the first transistor Q2□ can always be 7VBF regardless of temperature changes. Figure 7 shows another embodiment. 5 shows the case where the polarities of the transistors in FIG. 5 are reversed. A compensating mother resistor It, □ is inserted to reduce the influence of the base current, and an output transistor QC5 is inserted to increase the emitter surface area and obtain a current gain.

この場合、各トランジスタQ21 1Q22 1Q23
に挿入されたエミッタ抵抗B−13・R14・It 1
.の比を1 : 1 : 0.5とし、且つ各トランジ
スタQ21 r Q1121 Q10のエミッタ面、債
比’tll:2とすると、Q、2およびQ2Sの各コレ
クタからの定電流出力はそれぞれ 1 =I十l 01lT1 0 IN ■。、T2= 2 (Io十I、N) となる。
In this case, each transistor Q21 1Q22 1Q23
Emitter resistor B-13・R14・It 1 inserted in
.. If the ratio of the transistors Q21, Q1121, and Q10 is 1:1:0.5, and the ratio of the emitter surface of each transistor Q21, Q1121, and Q10 is 'tll:2, then the constant current output from each collector of Q, 2, and Q2S is 1 = I, respectively. 10l 01lT1 0 IN ■. , T2= 2 (Io×I, N).

第8図も°また他の実施例を示すもので、差動対トラン
ジスタQ311Q32の出力型Mtヲカレントミラ一対
トランゾスタQ331Q35およびQ341Q36でお
シ返した後、トランジスタQ36゜Q38でその差電流
を生成して負荷抵抗RLに供給することによシ、電圧出
力に変踏した場合である。
FIG. 8 also shows another embodiment, in which the output type Mt current mirror of the differential pair transistors Q311Q32 is returned by a pair of transistors Q331Q35 and Q341Q36, and the difference current is generated by the transistors Q36 and Q38 to load the load. This is a case where the voltage output is changed by supplying the voltage to the resistor RL.

なお、この発明は上記し且つ図示した実施例のみに限定
されることなく、この発明の安打を逸脱しない範囲で種
々の変形や適用が可能であることは言う迄もない。
It goes without saying that the present invention is not limited to the embodiments described above and illustrated, and that various modifications and applications can be made without departing from the scope of the present invention.

〔発明の効果〕〔Effect of the invention〕

従って、以上詳述したようにこの発明によれば、可及的
に簡易な構成で電源電圧が1v以下の如き低電圧動作化
を図ることが容易に可能となるように改良した極めて良
好なカレントミラー回路を提供することができる。
Therefore, as described in detail above, according to the present invention, an extremely good current current is improved so as to easily achieve low voltage operation with a power supply voltage of 1 V or less with the simplest possible configuration. A mirror circuit can be provided.

【図面の簡単な説明】 第1図乃至第4図は従来のカレントミラー回路を示す構
成説明図、第5図乃至第8図はこの発明に係るカレント
ミラー回路の一実施例および他の実施例を示す構成説明
図である。 (Jzt+Qzz ・・・ トランジスタ、IIN・・
・入力端子源、vcc・・・電源、RLl・・・抵抗、
GND・・・基準電位点、Io・・・定電流源。 出願人代理人 弁理士 鈴 江 武 彦第1図 第3図 第2図 第4図 第5図 第6図
[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 4 are configuration explanatory diagrams showing conventional current mirror circuits, and FIGS. 5 to 8 show one embodiment and other embodiments of the current mirror circuit according to the present invention. FIG. (Jzt+Qzz...transistor, IIN...
・Input terminal source, vcc...power supply, RLl...resistance,
GND: Reference potential point, Io: Constant current source. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 2 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 各エミッタが基準電位点または電源に接続されると共に
各ベースが互いに共通に接続された第1および第2のト
ランジスタと、これら第1および第2のトランジスタの
共通ベースと電源または基準電位点間に接続された定電
流源と、前記第1のトランジスタのベース・コレクタ間
に接続された抵抗とを具備し、前記定電流源および抵抗
とによシ前記第1のトランジスタのコレクタ電位をベー
ス電位よシも低く設定すると共に、前記第1のトランジ
スタのコレクタに入力電流を供給し、且つ前記第2のト
ランジスタのコレクタから出力電流を導出するように構
成したことを特徴とするカレントミラー回路。
first and second transistors, each emitter of which is connected to a reference potential point or a power source, and each base of which is commonly connected to each other, and between the common bases of the first and second transistors and the power source or reference potential point; A constant current source connected to the base and a resistor connected between the base and collector of the first transistor are provided, and the collector potential of the first transistor is changed from the base potential by the constant current source and the resistor. 1. A current mirror circuit, characterized in that the current mirror circuit is configured to supply an input current to the collector of the first transistor, and to derive an output current from the collector of the second transistor.
JP58142828A 1983-08-04 1983-08-04 Current mirror circuit Granted JPS6033717A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58142828A JPS6033717A (en) 1983-08-04 1983-08-04 Current mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58142828A JPS6033717A (en) 1983-08-04 1983-08-04 Current mirror circuit

Publications (2)

Publication Number Publication Date
JPS6033717A true JPS6033717A (en) 1985-02-21
JPH0151207B2 JPH0151207B2 (en) 1989-11-02

Family

ID=15324559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58142828A Granted JPS6033717A (en) 1983-08-04 1983-08-04 Current mirror circuit

Country Status (1)

Country Link
JP (1) JPS6033717A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3604530A1 (en) * 1985-02-14 1986-08-21 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa CURRENT MIRROR SWITCHING
US4897614A (en) * 1987-07-17 1990-01-30 Kabushiki Kaisha Toshiba Current mirror circuit
US5721512A (en) * 1996-04-23 1998-02-24 Analog Devices, Inc. Current mirror with input voltage set by saturated collector-emitter voltage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5335350A (en) * 1976-09-13 1978-04-01 Hitachi Ltd Current mirror circuit
JPS5367335A (en) * 1976-11-27 1978-06-15 Mitsubishi Electric Corp Integrated circuit formation current matching circuit
JPS5536662U (en) * 1978-08-31 1980-03-08

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5335350A (en) * 1976-09-13 1978-04-01 Hitachi Ltd Current mirror circuit
JPS5367335A (en) * 1976-11-27 1978-06-15 Mitsubishi Electric Corp Integrated circuit formation current matching circuit
JPS5536662U (en) * 1978-08-31 1980-03-08

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3604530A1 (en) * 1985-02-14 1986-08-21 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa CURRENT MIRROR SWITCHING
DE3604530C2 (en) * 1985-02-14 1988-07-28 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa, Jp
US4897614A (en) * 1987-07-17 1990-01-30 Kabushiki Kaisha Toshiba Current mirror circuit
US5721512A (en) * 1996-04-23 1998-02-24 Analog Devices, Inc. Current mirror with input voltage set by saturated collector-emitter voltage

Also Published As

Publication number Publication date
JPH0151207B2 (en) 1989-11-02

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