JPS58119651A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the yield rate of production, to microscopically form the isolation width between wirings and electrodes as well as to simplify the manufacture of the high density conductive wiring for the titled semiconductor device by a method wherein the stepping on the surface is eliminated and the type of coating and the disconnection of the insulating film to be formed thereon is improved. CONSTITUTION:A V-shaped groove 19 is formed by performing an ethcing on a part of Si films 18 and 18', and the polycrystalline Si layer 15 for gate elecctrode and the Si film 18 for wiring are isolated. Then, the exposed surface of the polycrystalline Si layer 15 and the Si film 18 are flattened by dissolving an Mo mask in the mixed solution of H2SO4 and H2O2 and also by performing a lift-off. The above is formed into a conductive layer having an N type conductivity by injecting an element from above said exposed surface, and, at the same time, the region which is isolated by the V-shpaed groove 19 on the main surface of the substrate 2 is formed into N type conductive regions 6 and 6'. Subsequently, a heat treatment is preformed, the element which was doped on the Si film 18 is diffused on the main surface of the Si substrate 2, and the N type conductive region 6 for source and the N type conductive region 6' for drain are formed. Then, an insulating film 20 is deposited on the whole surface of the substrate having a gate electrode 5 and wirings 7 and 9 by performing a thermal decomposition method, a sputtering method or an ECR type plasma deposition method, and the V- shaped groove is buried, thereby enabling to obtain a flat surface of the SiO2 film 20 without the V-shaped groove.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to a semiconductor device having a flat semiconductor element surface and high-density conductive wiring, and a method for manufacturing the same.

First, a typical configuration example of the prior art will be explained using drawings, and its problems will be described.

Figures 1fa to 1d are cross-sectional views for explaining the main steps of a conventional MOS transistor manufacturing method.
Figure 1(d) shows the completed structure of the main part. In the figure, 1 is a l\40S transistor, 2 is a semiconductor substrate (p-type single crystal Si substrate), 6 is an isolation region (1 thick 5i024), and 6' is an Si whose thickness changes continuously.
() 2 films, 4 is an insulating film (gate oxide film), 5 is a gate electrode, 6 and 6' are n conductivity type regions for source and drain (n+ expansion layer), 7 and 9 are wirings formed of conductive material (electrode), 8 is an insulating film, and 10 is a contact hole. The element isolation region 6 is provided to electrically insulate the MOS transistor 1 from other transistors, and is a commonly used element isolation method. Since this inter-element isolation: +(t V (thick 5102 model) 3 is formed by selectively thermally oxidizing the surface of the S+ substrate 20 using the oxidation-resistant film as a mask, this inter-element isolation method is a selective oxidation method. It is called.

The first step is to manufacture a MOS transistor with such a structure.
As shown in FIG. 1(a), an insulating film 8 is formed on the main surface of the semiconductor, and then, as shown in FIG. 1(b), contact holes 10 are formed in predetermined holes by etching. Next, a conductive material 1t911 is formed on the surface of the insulating film 8, and as shown in FIG.
) obtain the structure shown. This is patterned by photoetching to form wiring (electrodes) 7.9, thereby obtaining the MOS transistor 1 shown in FIG. 1 (Td).

Since the contact hole 10 is formed by etching a predetermined region of the insulating film 8 in this way, the n+ diffusion layer 6.
When the wiring 7.9 is formed on the contact hole 10 on the surface of the transistor 1, the film thickness of the wiring 7, 9 becomes non-uniform, and the gate electrode 5 and the insulating film 8 are formed on the surface of the +VO8) transistor 1. Irregularities are formed depending on the thickness. Further, since the insulating film 8 also has a step portion raised by the thickness of the gate electrode 5, the patterning accuracy of the wirings 7 and 9 formed on the insulating film 8 is reduced.

However, in such a MOS transistor structure, disconnection of wiring or poor contact occurs at the stage 9 part, and the resistance value tends to vary. In addition, total diffusion layer 6.6' and wiring 7.9
Poor contact is likely to occur between the Fourth, the process of forming the contact hole 11J requires a high degree of precision, resulting in problems such as a low manufacturing yield of semiconductor devices.

FIG. 2 is a cross-sectional view for explaining the main structure of a conventional MOS dynamic memory cell. In the figures, the same reference numerals as those mentioned above indicate the same or equivalent parts. 6'' is an n+ diffusion layer for a bit line, 12 is a wiring for a word line, and 13 is, for example, a multilayer.

MOS capacitor electrode formed of crystalline silicon, 14
is insulating, very strong.

The advantage of the memory cell with this structure is that the positioning margin of the contact hole 10 for the word line can be expanded, and the separation width between the word line wiring (conductive material) 12 and the MO'S cavantor electrode 16 improves the alignment accuracy. This means that it can be miniaturized without any interference.

However, this memory cell structure has the following drawbacks.

That is, the word line wiring 12 is deposited directly on the gates 1 and 4, and is also deposited on the MOS capacitor electrode 16 with an insulating film 14 interposed therebetween. When a conductive material layer (wiring part) 11 is formed on the wiring 12 through the contact hole 10, a MOS capacitor electrode 16 and an insulating film 14 are formed on the surface of the memory cell.
and irregularities corresponding to the thickness of the word line wiring 12 are formed,
The thickness of the conductive material layer 11 becomes non-uniform, making wire breakage more likely to occur.

The present invention has been made in order to solve these problems, and provides a semiconductor device in which the surfaces of wiring and electrodes have flat exposed portions, and the width of separation between wirings and electrodes can be miniaturized. Its first purpose is to provide a novel LSI with a flat device surface and high-density wiring. A second object is to provide a manufacturing method that can easily realize the device of the present invention.

Hereinafter, the present invention will be explained in detail with reference to examples.In order to simplify the explanation, the materials of each part and the conductivity type of the semiconductor will be specified and explained, but the present invention is not limited to these. Of course, the present invention is also applicable to cases where the material is changed, the conductivity type or the polarity of the applied voltage is reversed.

FIGS. 6fa) to 6(f) show the first part of the semiconductor device according to the present invention.
This is a cross-sectional view for explaining the main step γ of the manufacturing method of the embodiment, and FIG.

The semiconductor device shown in FIG. 6(f) corresponds to the structure of No. 11q(d) explained in the prior art, and has a gate oxide film on the main surface of the p-type single crystal 8i7) substrate 2. A conductive electrode 5 formed of a conductive material (for example, polycrystalline silicon) is formed through the conductive layer 4, and is deposited directly on the source n-conductivity type region B formed on the main surface of the substrate to form an electrical contact. A wiring 7 made of a material and a wiring 9 made of a conductive material deposited directly on the drain n-conductivity type region 6' to form an electrical contact are provided. With this configuration, it is possible to easily flatten the exposed surfaces of the wirings and electrodes and to reduce the separation width between the gate electrodes and the wiring paths.

Next, the method for manufacturing the semiconductor device of the present invention will be described in accordance with the order of the drawings in FIG.

First, from the main surface of the substrate 2 of the famp type single crystal 8i,
5102 film is deposited by ion beam sputtering, ECR type plasma deposition, etc. according to the etching depth (for example, about 1 μm), and then the MO mask is dissolved and etched by a lift-off method. S deposited in the untreated area (on the Mo mask)
By removing the i02 layer, an inter-element isolation region (thick Si02 film) 3 is formed. Next, the substrate surface is thermally oxidized to form an insulating film (8i02 film, gate oxide film) 4, and a polycrystalline Si layer (becomes the first conductive material layer) 15.
form. On this polycrystalline S1 layer 15, high melting point metal Mo
A pattern 16 of the gate electrode is formed by depositing by sputtering, vapor deposition, etc., and photoetching.

(b): The polycrystalline Si layer 15 and the 5I02 layer (gate oxide film) 4 not covered with the baton (Mo mask) 16 are etched to expose the main surface 17 of the substrate 2 fpl.

(C): An 8i film (becoming a second conductive material layer) 18, 18' is deposited on the surface of the substrate 20 including the Mo mask 16 and the portion left after the etching process by sputtering, ECR plasma deposition, etc. It is deposited using the following deposition method.

In this example, an ECR type plasma deposition method was used because this method makes use of the directionality of the plasma, and the Si film 18' attached to the sidewall of the portion left behind by the mask and etching process. This is because the film quality is less likely to be activated during deposition, resulting in an 8i film containing impurities, making it easier to form the figure-7 groove in the subsequent etching step.

(d): Part of the Si film is etched. In this example, isotropic etching and etching were performed using a hydronic acid-based etching solution. 8 attached to the side wall compared to the Si film 18.
Since the etching speed of the i-film 18' is faster, a V-shaped groove 19 is formed through this process, and the polycrystalline S for the gate electrode is
The i layer 15 and the 8i wiring film 18 are separated.

fe): Mo mask 16 with H2804/H2O2
Dissolve the mixture and lift it on. Since the Mo film undergoes side etching at a rate of about 70 μm/min in the above-mentioned mixed solution, lift-off can be easily performed even over a large area. Through this process, the polycrystalline Si layer 15 (gate electrode 5) and the 81 film 18 (
A structure is obtained in which the exposed surface of the wiring 7.9) has a flat surface. Using ion implantation technology, an element that imparts n-type conductivity to 8i is implanted onto the polycrystalline Si layer 1.
The 5 and 8i films 18 are made to be conductive material layers having n-type conductivity, and at the same time, the regions separated by the V-shaped groove 19 on the main surface of the substrate 2 are made to be n-type conductive regions 6 and 6'.

(f): If heat treatment is performed by selecting the optimum temperature for the process in the temperature range of about 700-1100℃, 8i
The elements doped in the film 18 are diffused into the main surface of the Si substrate 2 to form an n-conductivity type region 6E for a source and an 1n-conductivity type region 6' for a drain. At the same time, the Si film 18 (wiring 7
, 9) and the n-conducting shadow region 6,6' of the Si substrate 2.

Next, an insulating film (Si02 film) 20 is deposited over the entire surface of the substrate including the gate electrode 5 and the wirings 7 and 9 by a thermal decomposition method, a sputtering method, or an ECR-type plasma deposition method. At this time 7
The top 20 of the groove 19 is filled with the S'i02 film 20, and the 5i
The surface of the 02 film 200 has a flat structure with no 7-shaped grooves.

The above steps constitute the main part of the n-channel field effect transistor.

In this example, Mo was used for the gate electrode pattern 16, but instead of Mo, W, Ti, Zr, Nb
These high melting point metals, or these high melting point metals containing oxygen or nitrogen may be used. The reason for using high melting point metals is that even if the lift-off yield is not 100% and some high melting point metal remains, it will not become a source of contamination during subsequent heat treatment such as the diffusion process (β), so high temperature processing is possible. Of course, it is also possible to perform lift-off using a photoresist instead of a high-melting point metal, but in this case, a perfect lift-off technique is required in terms of yield.

FIGS. 4(a) to 4(k) show the second structure of the semiconductor device according to the present invention.
This figure is a cross-sectional view showing the manufacturing method of the example in order of steps.
Figure k) shows the structure of the main part of the completed one-transistor type memory cell.

The semiconductor device shown in FIG. 4(k) corresponds to the structure shown in FIG.
A word line wiring (electrode) 12 formed of a conductive material and an electrode 13 for a MOS capacitor are formed on the main surface of the substrate via an insulating film (gate oxide film) 4, and an n-conductivity type region formed on the main surface of the substrate. A bit line wiring (electrode) 21 is provided to form an electrical contact using a conductive material deposited directly on the cutout 6.

As can be seen from the figure, the exposed surfaces of each electrode and wiring have been flattened and separated finely.

Next, the method for manufacturing the semiconductor device of the present invention will be described in accordance with the order of the drawings in FIG.

(a): Inter-element isolation region (thick 5i02 film) 3. on the main surface of the single-crystal Si substrate 2. An insulating film (SiO2 film, gate oxide film) 4 and a polycrystalline 81 layer 15 (which will become a first conductive material layer) are formed. On this polycrystalline Si layer 15, a pattern 16 for forming a capacitor electrode 13 is provided using high melting point metal Mo.

11] Etch the polycrystalline Si layer 15 that is not covered with the pattern (MO mask) 16, and
The surface of the iO2 layer (gate oxide film) 4 is exposed.

(C): An 8i film (second (conducting material layer) 18.18' is sputtered on the surface of the substrate 20, which covers the mask 16 of \40 and the portion left by the etching process).

1.: CH, t (deposited by a deposition method such as q plasma deposition method).

(d) When a part of the S1 film is isotropically etched, the etching rate of the Si film 18'' attached to the side wall is lower than that of the Si film 18, so a V-shaped groove 19 is formed. The polycrystalline Si layer 15 and the SI pattern 18 are separated.

(,2) Small 7-sk 16 l-12804/H2
Dissolve and lift-off in O2 mixed solution. After lift-off, the sides and shells are separated from each other by 7-figure 4-1-9, and the exposed surface is approximately 15 and 8.
The i film 18 is clear. The steps up to this point are almost the same as those described in the first embodiment [Figs. 6(, 4) to (e)].

('') A pattern (mask) 16' of \10 is provided for forming the word line wiring (electrode) 12.

(g): The portions of the 8i film 18 and the 5i02i1 film 4 not covered by the Mo mask 16' are etched to expose the main surface 17 of the substrate 2. This process is the same as the 5th National Electric Railway).

(h): Si + Kan 18″, 18″’ on the entire surface
Deposit. This step is the same as that shown in FIG. 6(C).

(1) 2 A part of the Si film is isotropically etched to form a V-shaped groove 19', and the bit line wiring (electrode) 21 is formed separately from the word line wiring (electrode) 12. This step is the same as that shown in FIG. 6(d).

(j): MO mask 16' by lift-off process
and the Si film 18'' deposited thereon are removed.Next, ions are implanted to impart n-type conductivity to each wiring (electrode), and at the same time, N-type conductivity is added to the substrate 2 at the V-groove 19 and 19' portions. 1. This process is shown in Figure 3 (
This is the same process as e).

(k): A 5i02 film (insulating film) 20 is deposited on the entire surface of the substrate having each wiring (electrode) by BCR, Ken plasma deposition method, etc., filling the 7-character 4p 19 + 19' and making a flat surface. We obtain a structure with . Thereafter, thermal texturing is performed at, for example, 900 to 1100°C in an inert gas. This F
No adventure! Station 11! LF) Si i 18" (wiring 21 for bit line) The electrical contact between the wiring (acoustic music) 21 and the n-conducting shadow region 6 becomes good.This process corresponds to the process shown in FIG. 6ff).

The rod constitutes the main branch of a one-transistor memory cell.

5th:<I (al to (f) are cross-sectional views showing the manufacturing method of the third <4 example (main part of an npn type bipolar transistor) of the semiconductor device according to the present invention in order of steps, and FIG. 51, comprising the steps of the present invention shown in
FIG. 2 is a cross-sectional view of a p n type bipolar transistor.

First, the structure will be explained using No. 61 A]. In the figure, 22 is a base electrode formed of an S1 film (conductive material) doped with B, and 26 is a Si.1 film doped with As or P.
24 is a conductive type resistor for the base, 25 is n'-41j' for the emitter,
26 is a p-conductivity type region for the base; 27 is a collector electrode shaped and made of 5IID (conductive material) doped with As or P; 28 is a collector electrode; 29 is a collector electrode of n-conductivity type;
．． 30 is the n1 guide city type P page Makoto for collectors.

As you can see from the diagram, this bipolar transistor is
A base electrode 22 formed of a conductive material directly on a semiconductor substrate having a flat principal surface. Since the emitter electrode 26 and the collector electrode 27 are deposited, the exposed surfaces of these electrodes can be flattened, and the separation width of each electrode can be easily reduced to a fine 11B by forming a 7-shape 419.19''. Furthermore, since the base contact can be formed sufficiently close to the emitter, the area occupied by the transistor can be reduced and the series resistance of the base can be reduced.

Furthermore, since the emitter and base are surrounded by oxide due to oxide separation, the space between the base and the collector becomes smaller.

Next, using FIG. 5 and corresponding to the drawings (a) to (r) in the order shown, the manufacturing method of the main parts of the bipolar transistor of the present invention will be explained.

(a): Inter-element isolation region (
A thick 5102 film) 3 and a p-conducting shadow region 26 are selectively formed, and a polycrystalline Si layer 15' doped with B is deposited thereon by low pressure CVD method or the like.

(b) On this polycrystalline Si layer 15', a high melting point Mo layer is formed.
A batten 16'' for forming a base electrode is formed by photo-etching. Next, the polycrystalline Si layer 15' not covered with the Mo mask is etched to expose the surface of the p-conductivity type region 26.

(C): - Si film 1f doped with P or As over the entire surface of the substrate including the portion left in the etching process described in
, 18NDI is deposited by a deposition method such as a sputtering method or an ECR type plasma deposition method.

(d) Isotropic etching is performed to form a V-shaped groove 19 to separate the Si film 18'' for the emitter electrode from the polycrystalline 81 layer 15' for the base electrode.

(e): H2804/H2O2 mixture Matane 100
Lift-on in H2O2 solution at about ℃. After lift-off, polycrystalline Si layer 15' is removed by heat treatment in an inert gas.
P or As in the B and S1 films I BLLIJ is diffused into the p conductive shadow region 26, and the p+ conductive type shadow region 2 for the base is formed.
4 and an n+ conductivity type region 25 for emitter is formed.

Through this process, a structure is obtained in which the exposed side surfaces of the emitter electrode 25 and the base electrode 22 are separated from each other by the V-shaped groove 19, and the exposed surfaces are formed in the same plane.

(f): On top of this, the V-shaped groove 19 is filled with a 5i02 film (insulating film; when performing multilayer wiring, it becomes an insulating film between the eyebrows) 20 by ECR type plasma deposition method, etc., and a structure having a flat surface is formed. obtain.

The above steps constitute the main part of the bipolar transistor.

FIG. 7 shows a fourth embodiment (a configuration example of electrodes and wiring) of a semiconductor device according to the present invention, in which (a) is a plan view and (b) is an A-A' in (a). FIG.

This semiconductor device includes a plurality of electrodes and wirings 31 formed of a conductive material deposited directly on the main surface of a flat semiconductor substrate 2 or on an insulating film provided on the semiconductor substrate, and an insulating layer formed of an insulating material. 32, the exposed surfaces of the electrode, wiring 31 and insulator layer 62 are formed on the same plane, and the plurality of electrodes and wiring 61 are respectively insulated by the V-shaped plate 19 and the insulator layer 32, and any It has a structure that can be easily patterned into an electrode shape or a wiring shape. The method for manufacturing this structure may be carried out in accordance with the steps in Examples 1 to 3 described above, so the explanation will be omitted.

As the conductive material for forming the above electrodes and wiring, in addition to semiconductors containing n-conductivity type or p-conductivity type impurities, high-melting point metals, polycrystalline silicon, refractory metal silicides, etc. can also be used. can.

As explained above, the semiconductor device of the present invention has the advantage of improving the manufacturing yield of the semiconductor device because there is no surface step, and the covering shape of the insulating film formed thereon and disconnection of wiring are improved. In addition, it has the advantage that the separation width between wirings and electrodes can be made sufficiently fine, and high-density conductive wiring can be easily achieved.

[Brief explanation of the drawing]

Figures 1 (a) to (d) are cross-sectional views for explaining the main steps of a conventional MoS transistor manufacturing method, and Figure 2 is a cross-sectional view for explaining the main structure of a conventional MOS dynamic memory cell. , Fig. 6(a) to (f), Fig. 4(a)
~(k) and FIGS. 5(a) to 5) are sectional views for explaining the main steps of the manufacturing method of the embodiment of the semiconductor device according to the present invention, respectively, and FIG. FIG. 7 shows the structure of an embodiment of the semiconductor device according to the present invention, in which (a) is a plan view and (b) is a cross-sectional view taken along the line A-A' in (a). It is. 1... Mo8) transistor 2... semiconductor substrate 6
...Inter-element isolation region (thick S 02 film) 4...
- Insulating film (Si02 film, gate oxide film) 5...Gate electrode 6, 6', 6''...n conductive shadow region (n+ diffusion layer) 7.9... Wiring (electrode) 8... Insulating film 1
0... Contact hole 11... Conductive material layer 1
2... Word line wiring (electrode) 13... MOS capacitor electrode 14... Insulating film 15.15'...
Polycrystalline Si layer 16°16', 16"...bang (
Mo mask) 17... Principal surface of substrate 18.18
', 1.8", 18"', 18", 1B""'
...Si film 19.19', 19''...7-shaped groove
20... Insulation 4 (5i() 2 films) 21... Bit line wiring (electrode) 22... Base electrode 23...
・Emitter electrode 24...Conductive type region for base 2
5... N+ conductivity type region for emitter 26... P conductivity type region for base 27... Collector electrode 28...
N conductivity type region for collector 29.30...n for collector
+ Conductive type area 61...Thunderstorm, wiring 32...Insulator layer patent applicant Nippon Telegraph and Telephone Public Corporation's representative patent attorney Junnosuke Nakamura Daiichi Ill Figure 3 Figure 6 1F4 Figure 4 Figure 5 Figure Figure 5) F6 Figures 1-7

Claims (5)

[Claims] (1) At least one of a plurality of wirings and electrodes formed of the same kind of conductive material or different kinds of conductive materials on the main surface of the semiconductor substrate or on the insulating film provided on the semiconductor substrate, Multiple wiring. A semiconductor characterized in that the side walls of adjacent portions of the electrodes are separated from each other by a seven-shaped groove formed by etching, and the exposed surfaces of the plurality of wirings and electrodes are substantially on the same plane. Device. (2) The semiconductor device according to claim 1, wherein at least one of the conductive materials is a semiconductor containing an n-conductivity type or a p-conductivity type impurity. (3) The semiconductor device according to claim 1, wherein at least one of the conductive materials is one of a refractory metal, polycrystalline silicon, or a refractory metal silicide. (4) forming a first conductive material 1- on the main surface of the semiconductor substrate or on an insulating film provided on the semiconductor substrate;
A step of etching the first conductive material layer or the first conductive material layer and the insulating film using a high melting point metal or resist as a mask, and etching the entire surface of the semiconductor substrate including the portion left behind by the mask and etching step. a step of forming a second conductive material layer; and a step of etching a part of the second conductive material layer to form a 7-shaped groove between the first and second conductive material layers to separate both the conductive material layers. and a step of dissolving the mask and removing the second conductive material layer on the mask. (5) In the step of forming the second conductive material layer, E
5. The method of manufacturing a semiconductor device according to claim 4, wherein a CR type plasma deposition method is used.