JPS58109971A - ベクトル演算処理方式 - Google Patents

ベクトル演算処理方式

Info

Publication number
JPS58109971A
JPS58109971A JP20837181A JP20837181A JPS58109971A JP S58109971 A JPS58109971 A JP S58109971A JP 20837181 A JP20837181 A JP 20837181A JP 20837181 A JP20837181 A JP 20837181A JP S58109971 A JPS58109971 A JP S58109971A
Authority
JP
Japan
Prior art keywords
data
element data
register
pipeline
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20837181A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62550B2 (enExample
Inventor
Isao Azuma
東　功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20837181A priority Critical patent/JPS58109971A/ja
Publication of JPS58109971A publication Critical patent/JPS58109971A/ja
Publication of JPS62550B2 publication Critical patent/JPS62550B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
JP20837181A 1981-12-23 1981-12-23 ベクトル演算処理方式 Granted JPS58109971A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20837181A JPS58109971A (ja) 1981-12-23 1981-12-23 ベクトル演算処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20837181A JPS58109971A (ja) 1981-12-23 1981-12-23 ベクトル演算処理方式

Publications (2)

Publication Number Publication Date
JPS58109971A true JPS58109971A (ja) 1983-06-30
JPS62550B2 JPS62550B2 (enExample) 1987-01-08

Family

ID=16555173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20837181A Granted JPS58109971A (ja) 1981-12-23 1981-12-23 ベクトル演算処理方式

Country Status (1)

Country Link
JP (1) JPS58109971A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01284970A (ja) * 1988-05-11 1989-11-16 Nec Corp イテレーション演算回路
JPH01284969A (ja) * 1988-05-11 1989-11-16 Nec Corp イテレーション演算回路
JPH0273248U (enExample) * 1988-11-25 1990-06-05
JPH02148145A (ja) * 1988-11-29 1990-06-07 Koufu Nippon Denki Kk ベクトル演算装置のチェック回路
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01284970A (ja) * 1988-05-11 1989-11-16 Nec Corp イテレーション演算回路
JPH01284969A (ja) * 1988-05-11 1989-11-16 Nec Corp イテレーション演算回路
JPH0273248U (enExample) * 1988-11-25 1990-06-05
JPH02148145A (ja) * 1988-11-29 1990-06-07 Koufu Nippon Denki Kk ベクトル演算装置のチェック回路
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations
WO2011083152A1 (en) 2010-01-07 2011-07-14 Linear Algebra Technologies Limited Hardware for performing arithmetic operations

Also Published As

Publication number Publication date
JPS62550B2 (enExample) 1987-01-08

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