JPS5810831A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5810831A
JPS5810831A JP11013781A JP11013781A JPS5810831A JP S5810831 A JPS5810831 A JP S5810831A JP 11013781 A JP11013781 A JP 11013781A JP 11013781 A JP11013781 A JP 11013781A JP S5810831 A JPS5810831 A JP S5810831A
Authority
JP
Japan
Prior art keywords
oxide film
field oxide
annealing
ion implantation
laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11013781A
Other languages
Japanese (ja)
Other versions
JPH035057B2 (en
Inventor
Seiichiro Kawamura
河村 誠一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11013781A priority Critical patent/JPS5810831A/en
Publication of JPS5810831A publication Critical patent/JPS5810831A/en
Publication of JPH035057B2 publication Critical patent/JPH035057B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To recover the property of an insulating film, to which ions are irradiated, and to improve yield on production of the semiconductor device by annealing the insulating film by a laser. CONSTITUTION:A field oxide film 2 is formed to the surface of a P type silicon substrate 1 and an element forming region is demarcated, a gate oxide film 3 and a gate electrode 4 are shaped to the element forming region, an N type impurity (As) 5 is introduced through an ion implantation method while using the field oxide 2 and the gate electrode 4 as masks, and source and drain regions 6, 7 are shaped. Laser beams 8 are irradiated, and scanned (an arrow lin 9) extending over the whole region of the field oxide film 2, thus annealing the field oxide film 2. The normal manufacturing process is conducted successively. Accordingly, various characteristics (such as an etching rate and the like) of the field oxide film are recovered.

Description

【発明の詳細な説明】 本発明社半導体装置の製造方法に関し、特にイオン注入
を施こされて変化した絶縁膜の性質を回復させる方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of restoring properties of an insulating film that have been changed by ion implantation.

近年に至りL8I、超I、8I等の半導体装置の製造工
程においてイオン注入法が多用されているが、このイオ
ン注入工程においてイオンの照射を受けた絶縁膜は薬品
に対する被エツチレートの増大、屈折率の変化、或いは
耐圧の低下等の現象が現れ、その九め珈々の不都合が生
じる。
In recent years, the ion implantation method has been widely used in the manufacturing process of semiconductor devices such as L8I, super I, and 8I, but the insulating film that is irradiated with ions in this ion implantation process has an increased etch rate with respect to chemicals and a refractive index. Phenomena such as a change in the voltage or a drop in withstand voltage occur, resulting in numerous inconveniences.

例えけMOS FACTの製造工程においては、P型シ
リコン基板表面にフィールド酸化膜を形成して素子形成
領域を画定し、この素子形成領域にゲート電極を設けた
後、フィールド酸化膜とゲート電極をマスクとしてイオ
ン注入法により砒素(As )をシリコン基&表面に注
入し、次いで基板表面を薬品で処理する等の方法により
清浄化する前処理工程を径て、高、温炉内でアニールを
施こし、注入されたAsを活性化してソース及びドレイ
ン領域を形成する。この間上記フィールド酸化g*Fi
イオン注入を受けて被エツチレートが増大し、次の前処
理工程におψて使用される弗rllcHF)系のエツチ
ング液により著しく厚さを減じる。そのため半導体装置
の製蛤歩留及び信頼度を低下きせるという問題がある。
For example, in the manufacturing process of MOS FACT, a field oxide film is formed on the surface of a P-type silicon substrate to define an element formation region, a gate electrode is provided in this element formation region, and then the field oxide film and gate electrode are masked. Arsenic (As) is injected into the silicon base and surface using the ion implantation method, followed by a pretreatment process in which the substrate surface is cleaned by a method such as treatment with chemicals, and then annealed in a high-temperature furnace. , the implanted As is activated to form source and drain regions. During this time, the above field oxidation g*Fi
After the ion implantation, the etched rate increases, and the thickness is significantly reduced by the FluorilcHF)-based etchant used in the next pretreatment step. Therefore, there is a problem that the production yield and reliability of semiconductor devices are reduced.

上述のイオン注入されて変化した絶縁膜の性質は、この
後に引き続く高温アニール工程でほぼ回復するものでは
あるが、このことは上記前処理工程を高温アニール工程
に先立って行なわねばならないため前述の間履点の解消
には何ら寄与しない。
The properties of the insulating film that have changed due to the above-mentioned ion implantation can be almost recovered by the subsequent high-temperature annealing process, but this is because the above-mentioned pretreatment process must be performed before the high-temperature annealing process. It does not contribute in any way to eliminating the track mark.

本発明の目的はイオン注入を受けて変化した絶縁膜の性
質を次工程以後を施こすに先立って回復させ得る半導体
装置の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the properties of an insulating film that have changed due to ion implantation can be restored prior to subsequent steps.

本発明の特徴は、イオン注入工程のあとにイオンの照射
を受けた絶縁膜をレーザビームを照射することによりア
ニールする工程を付加し、しかる後に以後の工程を施こ
すことにある。
A feature of the present invention is that after the ion implantation step, a step of annealing the ion-irradiated insulating film by irradiating it with a laser beam is added, and subsequent steps are then performed.

以下本発明の一実施例を図面により説明する0IIh1
図〜第8図は本発明の一実施例を示す要部1lllr面
図及びl!部上面図、第4図(a)〜(C)は上記一実
施例の効果を示す曲線図である。
0IIh1 An embodiment of the present invention will be explained below with reference to drawings.
Figures 1 to 8 are side views of main parts showing one embodiment of the present invention, and 1! The top view of FIGS. 4(a) to 4(C) are curve diagrams showing the effects of the above embodiment.

第1図において、IFiPmのシリコン基板、2社フィ
ールド鹸化膜、8社ゲーl酸化膜、4はゲート電極であ
って、P型シリコン基板1表面にフィールド酸化M2を
形成して素子形成領域を画定し、この素子形成領域にゲ
ート酸化膜8とその上、にゲート電極4を形成した後、
上記フィールド酸化膜2及びゲート1!権4をマスクと
してイオン注入法により加速電圧凡そ150(Key)
で砒素(As)t2X10  (01”)程度シリコン
基板1表面ニ注入(矢線5)する。同図において6及び
7FiAsが注入された領域である。
In FIG. 1, a silicon substrate of IFiPm, a field saponification film of 2nd Company, a gale oxide film of 8th Company, 4 is a gate electrode, and a field oxide M2 is formed on the surface of a P-type silicon substrate 1 to define an element formation region. After forming a gate oxide film 8 in this element formation region and a gate electrode 4 thereon,
The above field oxide film 2 and gate 1! Acceleration voltage is approximately 150 (Key) by ion implantation using Key 4 as a mask.
Arsenic (As) of approximately t2X10 (01'') is implanted into the surface of the silicon substrate 1 (arrow line 5). In the same figure, this is the region where 6 and 7 FiAs are implanted.

上記工程においてフィールド酸化膜2は、当該部分のシ
リコン基板表面にAsイオンが注入されるのを阻止する
ためのマスクとして使用され、従って直接イオンの照射
を受ける。そのため弗#(HF)に対する被エツチレー
トが大幅に増大する等、フィールド酸化膜2の性質が変
化する。
In the above process, the field oxide film 2 is used as a mask to prevent As ions from being implanted into the surface of the silicon substrate at the relevant portion, and is therefore directly irradiated with ions. As a result, the properties of the field oxide film 2 change, such as a significant increase in the etching rate for HF.

そこで第2図に示す如くレーザビーム8を照射し、フィ
ールド酸化膜2全域にわたって走査(矢[9)すること
によりフィールド−化膜2のアニールを行なう。このレ
ーザアニールを実施するに当り、本実弛例ではシリコン
基板lを凡そ500(’(aに加熱しておき、連続発振
型式のアルゴン(Ar )乏 レーザを用い、出力を約tBw)、)4査速度は約10
〔cM/秒〕、走査軌跡のオーバラップ−は約80〔%
〕の条件を選択した。
Therefore, as shown in FIG. 2, the field oxidation film 2 is annealed by irradiating a laser beam 8 and scanning the entire field oxide film 2 (arrow [9)]. In carrying out this laser annealing, in this practical example, the silicon substrate 1 is heated to approximately 500 mA, and a continuous wave type argon (Ar)-poor laser is used, with an output of approximately tBw. 4 scan speed is about 10
[cM/sec], overlap of scanning trajectories is approximately 80 [%]
] was selected.

上述の条件のうち、基板lをIJu熱するのはレーザ出
力の不足を補なうためで、大出力レーザを用いて基板加
熱を省略してもよく、またパルス発振型式のレーザを使
用することも可能であるがレーザアニール後の絶縁膜表
面を荒らす場合があり、従って連続発振型式のレーザを
用いる方が好ましいようである。
Among the above conditions, the reason for heating the substrate l by IJu is to compensate for the lack of laser output, and it is also possible to omit substrate heating by using a high-output laser, or to use a pulse oscillation type laser. is also possible, but the surface of the insulating film after laser annealing may be roughened, so it seems preferable to use a continuous wave laser.

また走査軌跡のオーバラップ量は、第8図に示すように
、隣接する2つの走査軌跡の輻Wに対する両者のオーバ
ラップ幅りの比で、良好なアニールを行なうにはオーバ
ラップ閂を60〔%〕以上、出来得れば80〔%〕程度
とすることが望ましい0以上によりフィールド酸化膜2
はほぼ元の性質に回復する。従ってこのあとの工程は通
常の製造方法に従って進めてよく、即ち弗酸(HF )
系の薬品により前処理を施こし、次いで高温アニールを
行なって前述の注入されたムSを活性化することにより
、前記領域6.7をそれぞれソース領域に形成する。
The amount of overlap between the scanning trajectories is the ratio of the overlap width of two adjacent scanning trajectories to the radius W of the two adjacent scanning trajectories, as shown in FIG. %] or more, preferably about 80[%] or more, the field oxide film 2
almost recovers to its original properties. Therefore, the subsequent steps can be carried out according to the usual manufacturing method, i.e. using hydrofluoric acid (HF).
The regions 6 and 7 are each formed as a source region by performing pretreatment with a chemical, followed by high-temperature annealing to activate the aforementioned implanted S.

このようにHF系の薬品を用いる+M@理工程を施こし
ても、本実施例ではフィールド酸化j1211既に被エ
ツチレートがほぼ通常の値に回復しているので極端に厚
さを減じることがない。
Even if the +M@process using HF-based chemicals is performed in this manner, the thickness will not be excessively reduced because the field oxidation J1211 has already recovered to its normal value in the etched rate in this embodiment.

次に本実施例の効果を第4図(a)〜(C)を用いて説
明する。同図(a)〜(C)はSiO□膜の各段階にお
ける赤外吸収特性を示す曲線図で、同図(a)はAsイ
オンを注入した直後、同図伽)及び(C)はそれぞれ上
記試料を前述した条件でレーザアニールを行なったもの
及び窒素(N2)雰囲気中にお−て温度約1000L℃
〕で80〔分〕程高温アニールを行なったものの赤外M
吸収特性を示す。
Next, the effects of this embodiment will be explained using FIGS. 4(a) to 4(C). Figures (a) to (C) are curve diagrams showing the infrared absorption characteristics of the SiO□ film at each stage. The above sample was laser annealed under the conditions described above and at a temperature of approximately 1000 L°C in a nitrogen (N2) atmosphere.
] Although high temperature annealing was performed for about 80 [minutes], the infrared M
Shows absorption properties.

71sイオンを注入した場合には同図(a)に見られる
如く、波長10.1Lμm〕において顕著な吸収特性が
現れる。これに上述の如くレーザアニール或いは高温ア
ニールを施こすどと同図Φ)及び(C)に見られる如く
いずれも顕著な吸収特性は消滅し、しかも両者ははは同
じ吸収特性を示す。このことは5in2膜の性質がレー
ザアニールによす高温アニールを施こした場合とほば同
程度に回復させ得ることを示す。一方上述の高温アニー
ル紮織こしたSi0g膜は、被エツチレート等の諸性質
がイオン注入を行なう前とほば同じであることは周知で
ある。従って以上によ抄イオン注入工程の直後にレーザ
アニールを施こした本実施例のフィールド鴫化膜2の諸
性質社、少なくとも高温アニールを施ζした場合と同程
度巡回復し得たことが理解されよう。
When 71s ions are implanted, remarkable absorption characteristics appear at a wavelength of 10.1 L μm, as shown in FIG. When this is subjected to laser annealing or high-temperature annealing as described above, the remarkable absorption characteristics disappear in both Φ) and (C) of the same figure, and moreover, both exhibit the same absorption characteristics. This shows that the properties of the 5in2 film can be recovered to almost the same extent as when high temperature annealing by laser annealing is performed. On the other hand, it is well known that the above-mentioned high-temperature annealed Si0g film has properties such as etching rate that are almost the same as before ion implantation. Therefore, it is understood that the various properties of the field atomized film 2 of this example, which was laser annealed immediately after the ion implantation process, were able to be recovered to at least the same extent as when high temperature annealing was performed. It will be.

以上説明した如く本発明によりイオン注入によシ変化し
た絹性質を、以後の工程を施こすに先立って回復させる
ことが可能となる。従って半導体装置の製造歩留及び信
頼度が向上する。
As explained above, according to the present invention, it is possible to restore silk properties that have been changed by ion implantation prior to performing subsequent steps. Therefore, the manufacturing yield and reliability of semiconductor devices are improved.

なお本発明は上記一実施例に限定されることなく、如何
なる絶縁膜についても適用し得るものであることは特に
説明するまでもない。
It goes without saying that the present invention is not limited to the above-mentioned embodiment and can be applied to any insulating film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第8図社本発明の一実施例を示す図で、第1図
、第2図Fi要部断面図、第8図はレーザビームの走査
軌跡を示す要部上面図、第4図(a)〜(C)は上記一
実施例の効果を説明するための赤外吸収特性を示す曲線
図である。 図において、1は半導体基板、2はフィールド(0) 第1図      翠 ← 則 第4図 一一寸蕩長(pm)
Figures 1 to 8 are diagrams showing an embodiment of the present invention, in which Figures 1 and 2 are sectional views of the main parts, Figure 8 is a top view of the main parts showing the scanning locus of the laser beam, and Figure 4 is a top view of the main parts showing the scanning locus of the laser beam. Figures (a) to (C) are curve diagrams showing infrared absorption characteristics for explaining the effects of the above embodiment. In the figure, 1 is the semiconductor substrate, 2 is the field (0).

Claims (1)

【特許請求の範囲】[Claims] 表面に絶縁膜を有する半導体基板に、所定のイオンを注
入する工程を含む半導体装置の製造方法において、前記
イオン注入工程に引吉続自前記イオン注入工程において
イオンの照射を受けた絶縁膜をレーザビームを照射する
ことによりアニールする工程を付加し、しかる後に以後
の工程を施こすことを特徴とする半導体装置の製造方法
In a method for manufacturing a semiconductor device, which includes a step of implanting predetermined ions into a semiconductor substrate having an insulating film on its surface, the insulating film that has been irradiated with ions in the ion implantation step is irradiated with a laser during the ion implantation step. 1. A method of manufacturing a semiconductor device, comprising adding a step of annealing by irradiating a beam, and then performing subsequent steps.
JP11013781A 1981-07-14 1981-07-14 Manufacture of semiconductor device Granted JPS5810831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11013781A JPS5810831A (en) 1981-07-14 1981-07-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11013781A JPS5810831A (en) 1981-07-14 1981-07-14 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5810831A true JPS5810831A (en) 1983-01-21
JPH035057B2 JPH035057B2 (en) 1991-01-24

Family

ID=14527960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11013781A Granted JPS5810831A (en) 1981-07-14 1981-07-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5810831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62210309A (en) * 1986-03-08 1987-09-16 Toshiba Electric Appliance Co Ltd Kerosene burning apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5562741A (en) * 1978-11-06 1980-05-12 Fujitsu Ltd Method of fabricating semiconductor device
JPS55111170A (en) * 1979-02-20 1980-08-27 Nec Corp Method of manufacturing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5562741A (en) * 1978-11-06 1980-05-12 Fujitsu Ltd Method of fabricating semiconductor device
JPS55111170A (en) * 1979-02-20 1980-08-27 Nec Corp Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62210309A (en) * 1986-03-08 1987-09-16 Toshiba Electric Appliance Co Ltd Kerosene burning apparatus
JPH0318083B2 (en) * 1986-03-08 1991-03-11 Toshiba Kiki Kk

Also Published As

Publication number Publication date
JPH035057B2 (en) 1991-01-24

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