JPS58121682A - Manufacture of double gate semiconductor element - Google Patents

Abstract

PURPOSE:To obtain an excellent double gate structure which does not cause recess of an insulating film between a control gate and a floating gate as well as between the floating gate and a semiconductor substrate by employing a dry etching type to etch an oxidized film. CONSTITUTION:An upper layer polysilicon layer 5 is selectively etched by carbon tetrafluoride/oxygen mixture gas plasma with a resist mask 6, thereby forming a control gate 5a. Subsequently, an oxidized film 4 is etched, as shown in Fig. (b) by a parallel flat plate type plasma etching device which employs tricarbon octafluoride gas, thereby forming an interlayer oxidized film 4a. Thereafter, a lower layer polysilicon layer 3 is, as shown in Fig. (c), plasma etched again with CF4/O2 mixture gas as a floating gate 3a, and the oxidized film 2 on the substrate is then etched again with C3F3 gas, thereby forming a gate oxidized film 2a. Then, the mask 6 is removed, as shown in Fig. (d), arsenic ions are implanted, are annealed in nitrogen atmosphere, thereby forming source and drain regions 7, and a thermally oxidized film 8 is eventually formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a double gate semiconductor confectionery used in floating gate type non-volatile memories, etc.
In particular, it relates to improvements in the method for forming the double gate structure.

Hereinafter, a method of manufacturing a 70-gate type nonvolatile memory device having a double-gate field effect transistor structure will be described as an example.

FIGS. 1(a) to 1(f) are cross-sectional views showing states at main process steps to explain a conventional manufacturing method.

First, as shown in the ag1 diagram (,), silicon substrate +1
A substrate oxide film (2), a lower polysilicon layer (3), an interlayer oxide film (4), and an upper polysilicon layer (5) each having a required thickness are formed on the substrate 1 in order, and a scanning body is prepared. A resist mask (6) having a predetermined pattern is formed on the upper polysilicon layer (6). Next, as shown in FIG. 1 (1), using this resist mask (6) as a mask, the upper polysilicon layer (5) is subjected to plasma etching to form a control gate (5 &). As shown in Figure 1 (C), the interlayer oxide film (4) is etched using a hydrofluoric acid solution using each of the above layers as a mask to form a formed interlayer oxide film (4a).The same procedure is followed thereafter. @1 As shown in Figure (d), the lower polysilicon m (a
) by plasma etching to create a 70-teing game) (
3a), and then, as shown in FIG. 1(e), oxidation on the substrate [(2) is etched with a 7-acid solution to form gate oxidation@(2a). Thereafter, the source and drain regions (7) are formed by phosphorous deposition or ion implantation as shown in FIG. This is the old-timer.

However, in the conventional method described above, when etching the interlayer oxide film (4) and the oxide film on the substrate (2) using hydrofluoric acid at $11, the etching is done in an isotropic manner.
This causes depressions as shown by A and B in Figure (e).

These recesses A and B are also retained in the final product, forming the floating gate (A) and source.

Threshold with drain (7) and control gate (5a) with 7
The insulation properties between the floating gate (3a) and the floating gate (5a) deteriorate, and the charge held in the floating gate (5a) is pulled out from the control gate (5&), source, and drain (7), resulting in poor charge retention properties. Become.

This invention was made in consideration of the above points, and by using a dry etching method for etching the oxide film, insulation is created between the control gate and the 70-ring gate and between the floating gate and the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a double-gate semiconductor device that does not cause film depressions.

#I2 Figures (a) to (d) are cross-sectional views showing the state of an embodiment of the present invention at the stage of main construction, and the same reference numerals as in the conventional example in Figure IX1 indicate the same or corresponding parts. First, as in the conventional example, an over-substrate oxide film (2) and a lower polysilicon layer (3) are formed on a silicon substrate (1), each having a required thickness.

The interlayer oxide film (4) and the upper polysilicon layer (5) are
The oxide film was formed by thermal oxidation, and the polysilicon layer was formed by OVD (Oh
emi-cal Vapor Deposition
) method, and as shown in #I2 figure (1), the resist mask (6)
Using
) The upper polysilicon layer (5) with a film thickness of 3500 Å is selectively etched using mixed gas plasma to selectively etch the control gate (5).
Form a). Next, as shown in FIG. 2 (1)), the interlayer oxide film (4) with a film thickness of 120 OA was etched using a nine-parallel plate plasma etching apparatus using tri-RIA (ollys) gas to remove the interlayer oxide film (4) between the formed layers. Oxidation 'Ill!
(4a). When we observed the cross section of a part of the sample in this state using a scanning microscope, we found that the control gate (5
No etching inward from the edge of a) was observed. Thereafter, as shown in FIG. 2(0), the lower polysilicon layer (3) is formed with a film thickness of 3500A using the OFηh mixed gas again.
Plasma etching and floating game) (3
Then, the oxide film (2) on the substrate having a film thickness of OOA is etched again using 0+IF and gas using a parallel plate plasma etching apparatus to form a gate oxide film (2&). After that, as shown in Fig. 2(d), 700W #
The resist mask (6) was etched for 60 minutes using a plasma etching device, and arsenic was etched at 5X 10”/
am” (1) Ion implantation into concentrated W, annealing in nitrogen (N*) at 1050° C. for 40 minutes to form source and drain regions (71), followed by O11 at 1050° C. It is oxidized in a gas for 8 minutes to form a well-prepared film (8).After that, the sample is taken out and its cross section is observed with a scanning microscope. No dents were formed at all.

Using the method of this example, a 32 kilobit floating gate type non-volatile memory was manufactured, and compared to that using the conventional method, the non-volatile properties in a high temperature storage test at 250"C were improved by about twice. 9. The phenomenon of charge extraction from the source and drain caused by the electric field has also been significantly improved.

In the above embodiment, 0aFs was used for etching the oxide film.
Although the method is not limited to the gas plasma etching method, a dry etching method such as plasma etching using another gas or sputter etching may also be used.

As detailed above, in the present invention, a dry etching method is used for etching the oxide film on the substrate and the interlayer oxide film in manufacturing a semiconductor device with a double gate structure. An excellent nine-double gate structure can be obtained and the properties of confectionery can be improved.

[Brief explanation of drawings]

Figures 1 (IL) and - (f) are cross-sectional views showing the main process steps of the conventional manufacturing method, Figures 2 (&) - (6)
FIG. 1 is a cross-sectional view showing the state of an embodiment of the present invention at main process steps. In the figure, (1) is a semiconductor substrate, (2) is an oxide film on the substrate, (2a) is a gate oxide film, (3) is a lower polysilicon layer, and (3a) is a 70-ring gate (second gate). , (4) is an interlayer oxide film, (4a) is a formed interlayer oxide film,
(5) is the upper polysilicon layer, (5a) is the control gate (
$1 gate), (6) is a mask layer. In addition, the same reference numerals in the figures indicate corresponding parts. Agent mtf Shin - (1 other person) Figure 1 Figure 2

Claims (3)

[Claims] (1) When manufacturing a double-gate semiconductor device using a substrate in which a substrate oxide film, a lower polysilicon layer, a two-layer secondary oxide film, and an upper polysilicon layer are sequentially formed on a semiconductor substrate, the above-mentioned upper layer A step of selectively performing plasma etching on the polysilicon layer using a required mask layer to form a first gate in a required pattern; selectively etching the interlayer oxide film using the mask layer and the gate of gg1 as a mask; forming an interlayer oxide film by selectively etching the lower polysilicon layer using the mask layer, the first gate, and the interlayer oxide film as a mask; a step of forming a gate, the mask layer, the first gate,
forming a gate oxide film by selectively performing dry etching on the oxide film on the substrate using the formed interlayer oxide film and the second gate as a mask; and removing the mask layer from above the first gate. A method for manufacturing a double gate semiconductor device, comprising a step of removing. (2) A method for manufacturing a double gate semiconductor device according to claim 1, characterized in that plasma etching is used for the dry etching. (3) A method for manufacturing a double gate semiconductor device according to claim 1, characterized in that sputter etching is used for the dry etching.