JPS58103154A - Formation of interlayer insulating film for polycrystalline silicon layers - Google Patents
Formation of interlayer insulating film for polycrystalline silicon layersInfo
- Publication number
- JPS58103154A JPS58103154A JP20289281A JP20289281A JPS58103154A JP S58103154 A JPS58103154 A JP S58103154A JP 20289281 A JP20289281 A JP 20289281A JP 20289281 A JP20289281 A JP 20289281A JP S58103154 A JPS58103154 A JP S58103154A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon layer
- insulating film
- interlayer insulating
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 76
- 239000010410 layer Substances 0.000 title claims abstract description 70
- 239000011229 interlayer Substances 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 239000007864 aqueous solution Substances 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 238000001020 plasma etching Methods 0.000 abstract description 4
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 abstract description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 3
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置における２層あるいはそれ以上の多
結晶シリコン層間絶縁膜形成方法に関し、その目的とす
るところは上層及び下層多結晶シリコンの層間に位置す
る絶縁膜の絶縁耐圧を向上せしめ、上層及び下層多結晶
シリコン間のリーク電流を減少することができる多結晶
シリコン層間絶２ −１
縁膜形成方法を提供することである。Detailed Description of the Invention The present invention relates to a method for forming an insulating film between two or more polycrystalline silicon layers in a semiconductor device, and its purpose is to insulate an insulating film located between upper and lower polycrystalline silicon layers. It is an object of the present invention to provide a method for forming a polycrystalline silicon interlayer insulation film that can improve breakdown voltage and reduce leakage current between upper and lower polycrystalline silicon layers.
初めに、従来技術の一例として２層多結晶シリコン構造
を有するＭＯ８型半導体集積回路の層間絶縁膜形成方法
について第１図（−）〜（ｄ）を照して詳細に説明する
。まず、シリコン基板１の上に、ＬＯＧＯＳプロセスと
呼ばれる局部酸化法によって形成した膜厚７０ｏｏへの
選択酸化膜２及び膜厚６６０人の第１ゲート酸化膜３を
覆うように被着した膜厚５０００人の第１（下層）多結
晶シリコン層４をホトレジスト６をマスクにして、ＣＦ
４ ガスによるプラズマエツチングを行う（第１図（ａ
））。First, as an example of the prior art, a method for forming an interlayer insulating film of an MO8 type semiconductor integrated circuit having a two-layer polycrystalline silicon structure will be described in detail with reference to FIGS. 1(-) to 1(d). First, a selective oxide film 2 with a thickness of 7000 mm was formed on a silicon substrate 1 by a local oxidation method called LOGOS process, and a film with a thickness of 5000 mm was deposited to cover the first gate oxide film 3 with a thickness of 660 mm. Using the photoresist 6 as a mask, the first (lower) polycrystalline silicon layer 4 is coated with CF.
4 Perform plasma etching using gas (see Figure 1 (a)
)).
次に、ホトレジスト６を剥離後、第１多結晶シリコン層
４をマスクにして第１ゲート酸化膜３を弗酸：弗化アン
モニウム系水溶液を用いてエツチングするＣＭ１図山図
中Ｑその後、第１多結晶シリコン層４上に絶縁膜６を形
成するために、例えば水蒸気中、９００℃で３０分間の
熱処理を施し、第１多結晶シリコン層４の表面を酸化す
る。この時、同時に基板１の露出部には第２ゲート酸化
膜７が形成される（第１図（Ｃ））。次に、第２（上層
）多３’ニー７
結晶シリコン層８を被着して後、ホトレジストをマスク
にして第２多結晶シリコン層８をＣＦ４ ガス中でプラ
ズマエツチングし、その後、これに使用したホトレジス
トを剥離することにより、上述の２層多結晶シリコン構
造を完成する（第１図（ｄ））。Next, after peeling off the photoresist 6, the first gate oxide film 3 is etched using a hydrofluoric acid/ammonium fluoride aqueous solution using the first polycrystalline silicon layer 4 as a mask. In order to form the insulating film 6 on the polycrystalline silicon layer 4, heat treatment is performed at 900° C. for 30 minutes in water vapor, for example, to oxidize the surface of the first polycrystalline silicon layer 4. At this time, a second gate oxide film 7 is simultaneously formed on the exposed portion of the substrate 1 (FIG. 1(C)). Next, after depositing a second (upper) polycrystalline silicon layer 8, the second polycrystalline silicon layer 8 is plasma etched in CF4 gas using a photoresist as a mask. By peeling off the photoresist, the above-mentioned two-layer polycrystalline silicon structure is completed (FIG. 1(d)).
しかしながら、このようにして形成される２層多結晶シ
リコン構造では層間絶縁膜の絶縁耐圧が必らずしも十分
でなく、第１多結晶シリコン層と第２多結晶シリコン層
間に流れるリーク電流が大きいという欠点がある。However, in the two-layer polycrystalline silicon structure formed in this way, the dielectric strength of the interlayer insulating film is not necessarily sufficient, and leakage current flows between the first polycrystalline silicon layer and the second polycrystalline silicon layer. It has the disadvantage of being large.
ところで、上記シリコン基板１上に酸化成長させる第２
ゲート酸化膜７の厚さを一定の値とすると、第１多結晶
シリコン層４の上面及び側面に成長する眉間絶縁膜６の
厚さは第１多結晶シリコン層４に含まれるリン濃度と熱
処理条件に依存する。By the way, the second layer grown by oxidation on the silicon substrate 1 is
Assuming that the thickness of the gate oxide film 7 is a constant value, the thickness of the glabella insulating film 6 that grows on the top and side surfaces of the first polycrystalline silicon layer 4 depends on the phosphorus concentration contained in the first polycrystalline silicon layer 4 and the heat treatment. Depends on conditions.
例えば、第１多結晶シリコン層４のシート抵抗が４５Ω
の場合、水蒸気中、９００℃の熱処理を３０分施すと、
第２ゲート酸化膜７の膜厚は６５０人であり、この時、
眉間絶縁膜６の厚さは第１多結晶シリコン層７の上面及
び側面で約１３００八である。For example, the sheet resistance of the first polycrystalline silicon layer 4 is 45Ω.
In the case of , heat treatment at 900℃ in steam for 30 minutes will result in
The thickness of the second gate oxide film 7 is 650 mm, and at this time,
The thickness of the glabella insulating film 6 on the top and side surfaces of the first polycrystalline silicon layer 7 is about 1300 mm.
−
しかしながら、第１多結晶シリコン層４のひさし状の先
端下側部分では多結晶シリコンの酸化反応が進み４く、
この部分での層間絶縁膜の厚さは約６０ＯＡとなる。ま
た、第１多結晶シリコン層４の上面と側面が交差する角
に成長する層間絶縁膜６の厚さも第１多結晶シリコン層
４の上面及び側面に成長する層間絶縁膜６の厚さと比較
して薄く、約８００八である。更に、熱処理の温度ある
いは多結晶シリコン層７のシート抵抗を変化させた場合
も、第１多結晶シリコン層７の下面と側面との交差する
角の下側部分に成長する絶縁膜の厚さが、第１多結晶シ
リコン層４のその他の部分に成長する絶縁膜の厚さと比
較して薄いだめに、この部分において層間絶縁膜６の破
壊が起り易く、絶縁耐圧低下の原因となっている。例え
ば、上述のような厚みの関係で層間絶縁膜では、第１多
結晶シリコン層４と第２多結晶シリコン層間８の耐圧は
約ａａＶであった。- However, the oxidation reaction of polycrystalline silicon progresses in the lower part of the eave-shaped tip of the first polycrystalline silicon layer 4,
The thickness of the interlayer insulating film at this portion is approximately 60 OA. Also, the thickness of the interlayer insulating film 6 grown at the corner where the upper surface and side surfaces of the first polycrystalline silicon layer 4 intersect is compared with the thickness of the interlayer insulating film 6 grown on the upper surface and side surfaces of the first polycrystalline silicon layer 4. It is thin and about 800 mm. Furthermore, even when the heat treatment temperature or the sheet resistance of the polycrystalline silicon layer 7 is changed, the thickness of the insulating film grown at the lower part of the corner where the lower surface and the side surface of the first polycrystalline silicon layer 7 intersect can be changed. Since the interlayer insulating film 6 is thinner than the thickness of the insulating film grown in other parts of the first polycrystalline silicon layer 4, breakdown of the interlayer insulating film 6 is likely to occur in this part, causing a decrease in dielectric strength voltage. For example, in the interlayer insulating film due to the above-mentioned thickness relationship, the breakdown voltage between the first polycrystalline silicon layer 4 and the second polycrystalline silicon layer 8 was about aaV.
本発明は上記従来の欠点を除去することのできる多結晶
シリコン層間絶縁膜形成方法を提供する６ ヘージ
ものであり、第１ゲート酸化膜エツチング時に生ずる第
１多結晶シリコン層のひさし状の突出部を除去し、第１
多結晶シリコン層の角部分の下の層間絶縁膜を厚くする
ことによって絶縁耐圧を向上させるところに特徴がある
。The present invention provides a method for forming a polycrystalline silicon interlayer insulating film that can eliminate the above-mentioned conventional drawbacks. and remove the first
The feature is that the dielectric breakdown voltage is improved by thickening the interlayer insulating film under the corner portions of the polycrystalline silicon layer.
以下、本発明にかかる多結晶シリコン層間絶縁膜形成方
法の一実施例について第２図（−）〜（−）を参照にし
て詳細に説明する。なお、第１図（−）〜（ｄ）の場合
と同一番号を付している。まず、シリコン基板１の上に
形成した膜厚７０００人の選択酸化膜２及び膜厚６５〇
への第１ゲート酸化膜３を覆うように被着した膜厚５０
００人、シート抵抗４６Ωの第１多結晶シリコン層４を
ホトレジスト５をマスクにしてＣＦ４ ガス中でプラズ
マエツチングする（第２図（ａ））。次に、ホトレジス
ト６を剥離後、第１多結晶シリコン層４をマスクにして
第１ゲート酸化膜３を弗酸：弗化アンモニウム水溶液を
用いてエツチングする（第２図（ｂ））。その後、第１
ゲート酸化膜エツチング時の横方向エツチングによって
生じた第１多結晶シリコン層４のひさし状の６ −１
突出部が消滅し、第１多結晶シリコン層下の第１ゲート
酸化膜３の一部が、例えば幅１０００八程度その第１多
結晶シリコン層４の側面先端から現われる程度に、硝酸
二部酸系水容液を用いて第１結晶シリコン層４をエツチ
ングする（第２図（Ｃ））。Hereinafter, an embodiment of the method for forming a polycrystalline silicon interlayer insulating film according to the present invention will be described in detail with reference to FIGS. Note that the same numbers as in the case of FIGS. 1(-) to (d) are given. First, a selective oxide film 2 with a thickness of 7,000 formed on a silicon substrate 1 and a first gate oxide film 3 with a thickness of 650 are deposited to cover the film with a thickness of 50.
The first polycrystalline silicon layer 4 having a sheet resistance of 46 Ω was plasma etched in CF4 gas using the photoresist 5 as a mask (FIG. 2(a)). Next, after peeling off the photoresist 6, the first gate oxide film 3 is etched using a hydrofluoric acid:ammonium fluoride aqueous solution using the first polycrystalline silicon layer 4 as a mask (FIG. 2(b)). Then the first
The eave-shaped 6-1 protrusion of the first polycrystalline silicon layer 4 caused by lateral etching during gate oxide film etching disappears, and a part of the first gate oxide film 3 under the first polycrystalline silicon layer is removed. For example, the first crystalline silicon layer 4 is etched using a nitric acid-based aqueous solution to the extent that a width of about 1000 mm is exposed from the tip of the side surface of the first polycrystalline silicon layer 4 (FIG. 2(C)). .
このエツチング工程により、同第１多結晶シリコン層４
の上面、側面交差部の角も好ましくエツチングされる。Through this etching process, the first polycrystalline silicon layer 4
The top surface and the corners of the side intersections are also preferably etched.
次に、例えば９００℃の水蒸気中で３０分間の熱処理を
施し、第１多結晶シリコン層４上に第２多結晶シリコン
層８に対する層間絶縁膜６及びシリコン基板１上に第２
ゲート酸化膜７を同時に形成する（第２図（ｄ））。こ
の後、第２多結晶シリコン層８を被着して後、ホトレジ
ストをマスクにして、第２多結晶シリコン層８をＣＦ４
ガス中でスラズマエッチングする。そして、ホトレジス
トを剥離して、所望の２層多結晶シリコン構造を完成さ
せる（第２図（ｅ））。Next, a heat treatment is performed for 30 minutes in water vapor at 900° C., for example, to form an interlayer insulating film 6 on the first polycrystalline silicon layer 4 for the second polycrystalline silicon layer 8 and a second film on the silicon substrate 1.
A gate oxide film 7 is formed at the same time (FIG. 2(d)). After this, after depositing the second polycrystalline silicon layer 8, the second polycrystalline silicon layer 8 is covered with CF4 using a photoresist as a mask.
Plasma etching in gas. Then, the photoresist is peeled off to complete the desired two-layer polycrystalline silicon structure (FIG. 2(e)).
本実施例の方法によれば、第１多結晶シリコン層４の上
面及び側面の層間絶縁膜６の膜厚は上記第１図示の従来
例の場合と同様に約１３００人であ７１＼−ノ
るが、第１多結晶シリコン層４の側面と下面とが交差す
る角の部分に成長する層間絶縁膜６の最小膜厚は約１ｏ
ｏｏ人であり、従来の方法で同様絶縁膜を形成した場合
の上述の従来例における最小膜厚よりも約４０ＯＡ厚い
。この理由は、従来方法と異なり層間絶縁膜６形成前に
第１結晶シリコン層４の下面と側面の交差する角の下側
部分に第１ゲート酸化膜３が存在しているために層間絶
縁膜６の極端に薄くなる部分がなくなっているだめであ
る。尚、第１多結晶シリコン層４の上面と側面の交差す
る角の部分に成長する絶縁膜の厚さは約８８０人となり
、従来方法の場合よりわずかに厚い膜厚である。ところ
で、第１多結晶シリコン層４と第２多結晶シリコン層８
との間の耐圧は層間絶縁膜６全体の膜厚が最も薄い部分
で決定されるとすると、本実施例の方法の場合、眉間絶
縁膜６全体の最小膜厚は約８８０八であり、従来方法を
用いた場合よりも２８０人厚い。実際、第１多結晶シリ
コン層４と第２多結晶シリコン層８との間の耐圧は約６
２Ｖあり、従来方法により製造した上述の従来例２層多
結晶シリコン構造のものよりも約１４Ｖ向上した。According to the method of this embodiment, the thickness of the interlayer insulating film 6 on the top and side surfaces of the first polycrystalline silicon layer 4 is approximately 1,300 and 71\-no. However, the minimum thickness of the interlayer insulating film 6 grown at the corner where the side surface and the bottom surface of the first polycrystalline silicon layer 4 intersect is approximately 10.
The thickness of the insulating film is about 40 OA thicker than the minimum film thickness in the above-mentioned conventional example when a similar insulating film is formed using the conventional method. The reason for this is that, unlike the conventional method, the first gate oxide film 3 is present at the lower part of the corner where the lower surface and the side surface of the first crystalline silicon layer 4 intersect before the formation of the interlayer insulating film 6. The extremely thin part of 6 is gone. The thickness of the insulating film grown at the corner where the top and side surfaces of the first polycrystalline silicon layer 4 intersect is approximately 880 mm, which is slightly thicker than in the conventional method. By the way, the first polycrystalline silicon layer 4 and the second polycrystalline silicon layer 8
If the breakdown voltage between the 280 people thicker than when using the method. In fact, the breakdown voltage between the first polycrystalline silicon layer 4 and the second polycrystalline silicon layer 8 is approximately 6
2V, which is approximately 14V higher than that of the conventional two-layer polycrystalline silicon structure manufactured by the conventional method.
尚、本方法では、第１ゲート酸化膜３のエツチングの際
に、横方向エッチレグによって生じた第１多結晶シリコ
ン層４のひさし状突出部を除去する工程で、硝酸二部酸
系水溶液を用いだが、同エツチングをＣＦ４ ガス中の
プラズマエツチングで実施した場合も、第１及び第２多
結晶シリコン層間の耐圧は約５０Ｖであシ、本方法を用
いた場合と同程度であった。In addition, in this method, in the step of removing the eave-like protrusion of the first polycrystalline silicon layer 4 caused by the lateral etching legs during etching of the first gate oxide film 3, a nitric acid dipartic acid-based aqueous solution is used. However, when the same etching was performed by plasma etching in CF4 gas, the withstand voltage between the first and second polycrystalline silicon layers was about 50V, which was about the same as when using this method.
以上、説明したように、本発明の多結晶シリコン層間絶
縁膜形成方法を用いて多結晶シリコン層間の絶縁膜を形
成すると従来の多層多結晶シリコン構造における絶縁耐
圧不足の問題を効果的に解決することが可能である。本
発明は２層多結晶シリコン構造の製造方法を例示して説
明しだが、本発明の方法は３層あるいはそれ以上の多層
結晶シリコン構造を有する半導体装置全般に適用できる
ものである。As explained above, forming an insulating film between polycrystalline silicon layers using the polycrystalline silicon interlayer insulating film forming method of the present invention effectively solves the problem of insufficient dielectric strength in the conventional multilayer polycrystalline silicon structure. Is possible. Although the present invention has been described by exemplifying a method for manufacturing a two-layer polycrystalline silicon structure, the method of the present invention is applicable to all semiconductor devices having a multilayer crystalline silicon structure of three or more layers.
９１・−７
第１図（−）〜（ｄ）は従来の多結晶シリコン層間絶縁
膜形成方法を示す工程図、第２図（、）〜（ｅ）は本発
明の一実施例における多結晶シリコン層間絶縁膜形成方
法を示す。
１・・・・・・シリコン基板、２・・・・・・選択酸化
膜、３・・・・・・第１ゲート酸化膜、４・・・・・・
第１（下層）多結晶シリコン層、６・・・・・・ホトレ
ジスト、６・・・・・・多結晶シリコン間の眉間絶縁膜
（酸化ケイ素瓦７・・・・・・第２ゲート酸化膜、８・
・・・・・第２（上層）多結晶シリコン層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ＩＩ
Ｉ図
（（ＩＩ91・-7 FIGS. 1(-) to (d) are process diagrams showing a conventional polycrystalline silicon interlayer insulating film forming method, and FIGS. 2(,) to (e) are polycrystalline silicon in an embodiment of the present invention. A method for forming a silicon interlayer insulating film is shown. 1...Silicon substrate, 2...Selective oxide film, 3...First gate oxide film, 4...
First (lower layer) polycrystalline silicon layer, 6... Photoresist, 6... Insulating film between eyebrows between polycrystalline silicon (silicon oxide tile 7... Second gate oxide film , 8・
...Second (upper) polycrystalline silicon layer. Name of agent: Patent attorney Toshio Nakao and one other person II
Figure I ((II
Claims (1)
層を選択的にエツチングする工程と、この多結晶シリコ
ン層をマスクにして上記半導体基板上の絶縁膜をエツチ
ングする工程と、上記絶縁膜のエツチングの際に形成さ
れた上記多結晶シリコン層のひさし状突出部を除去する
工程と、上記多結晶シリコン層上に熱酸化によシ絶縁膜
を形成する工程とをそなえたことを特徴とする多結晶シ
リコン層間絶縁膜形成方法。a step of selectively etching a polycrystalline silicon layer formed on an insulating film on a semiconductor substrate; a step of etching the insulating film on the semiconductor substrate using the polycrystalline silicon layer as a mask; and a step of etching the insulating film on the semiconductor substrate. The method is characterized by comprising the steps of: removing the eaves-like protrusion of the polycrystalline silicon layer formed during etching; and forming an insulating film by thermal oxidation on the polycrystalline silicon layer. A method for forming a polycrystalline silicon interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20289281A JPS58103154A (en) | 1981-12-15 | 1981-12-15 | Formation of interlayer insulating film for polycrystalline silicon layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20289281A JPS58103154A (en) | 1981-12-15 | 1981-12-15 | Formation of interlayer insulating film for polycrystalline silicon layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58103154A true JPS58103154A (en) | 1983-06-20 |
| JPS6248379B2 JPS6248379B2 (en) | 1987-10-13 |
Family
ID=16464923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20289281A Granted JPS58103154A (en) | 1981-12-15 | 1981-12-15 | Formation of interlayer insulating film for polycrystalline silicon layers |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58103154A (en) |
-
1981
- 1981-12-15 JP JP20289281A patent/JPS58103154A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6248379B2 (en) | 1987-10-13 |
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