JPS5810226A - デ−タ処理装置 - Google Patents

デ−タ処理装置

Info

Publication number
JPS5810226A
JPS5810226A JP56109019A JP10901981A JPS5810226A JP S5810226 A JPS5810226 A JP S5810226A JP 56109019 A JP56109019 A JP 56109019A JP 10901981 A JP10901981 A JP 10901981A JP S5810226 A JPS5810226 A JP S5810226A
Authority
JP
Japan
Prior art keywords
processor
dma
machine cycle
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56109019A
Other languages
English (en)
Japanese (ja)
Other versions
JPH023217B2 (enrdf_load_stackoverflow
Inventor
Yasuo Nagai
永井　康生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56109019A priority Critical patent/JPS5810226A/ja
Publication of JPS5810226A publication Critical patent/JPS5810226A/ja
Publication of JPH023217B2 publication Critical patent/JPH023217B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
JP56109019A 1981-07-13 1981-07-13 デ−タ処理装置 Granted JPS5810226A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56109019A JPS5810226A (ja) 1981-07-13 1981-07-13 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56109019A JPS5810226A (ja) 1981-07-13 1981-07-13 デ−タ処理装置

Publications (2)

Publication Number Publication Date
JPS5810226A true JPS5810226A (ja) 1983-01-20
JPH023217B2 JPH023217B2 (enrdf_load_stackoverflow) 1990-01-22

Family

ID=14499520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56109019A Granted JPS5810226A (ja) 1981-07-13 1981-07-13 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS5810226A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183667A (ja) * 1984-03-02 1985-09-19 Nec Corp 情報処理装置
JPS60183663A (ja) * 1984-03-02 1985-09-19 Nec Corp 情報処理装置
JPS60183661A (ja) * 1984-03-02 1985-09-19 Nec Corp 情報処理装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183667A (ja) * 1984-03-02 1985-09-19 Nec Corp 情報処理装置
JPS60183663A (ja) * 1984-03-02 1985-09-19 Nec Corp 情報処理装置
JPS60183661A (ja) * 1984-03-02 1985-09-19 Nec Corp 情報処理装置

Also Published As

Publication number Publication date
JPH023217B2 (enrdf_load_stackoverflow) 1990-01-22

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