JPS5796518A - Method of forming polycrystalline silicon layer - Google Patents

Method of forming polycrystalline silicon layer

Info

Publication number
JPS5796518A
JPS5796518A JP56164353A JP16435381A JPS5796518A JP S5796518 A JPS5796518 A JP S5796518A JP 56164353 A JP56164353 A JP 56164353A JP 16435381 A JP16435381 A JP 16435381A JP S5796518 A JPS5796518 A JP S5796518A
Authority
JP
Japan
Prior art keywords
silicon layer
polycrystalline silicon
forming polycrystalline
forming
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56164353A
Other languages
English (en)
Other versions
JPS647488B2 (ja
Inventor
Yangu Dou Ben
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5796518A publication Critical patent/JPS5796518A/ja
Publication of JPS647488B2 publication Critical patent/JPS647488B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/123—Polycrystalline diffuse anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/164—Three dimensional processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
JP56164353A 1980-11-03 1981-10-16 Method of forming polycrystalline silicon layer Granted JPS5796518A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/203,039 US4358326A (en) 1980-11-03 1980-11-03 Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing

Publications (2)

Publication Number Publication Date
JPS5796518A true JPS5796518A (en) 1982-06-15
JPS647488B2 JPS647488B2 (ja) 1989-02-09

Family

ID=22752213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56164353A Granted JPS5796518A (en) 1980-11-03 1981-10-16 Method of forming polycrystalline silicon layer

Country Status (4)

Country Link
US (1) US4358326A (ja)
EP (1) EP0051249B1 (ja)
JP (1) JPS5796518A (ja)
DE (1) DE3176714D1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6448411A (en) * 1987-08-18 1989-02-22 Fujitsu Ltd Forming method of polysilicon layer
JPH01129465A (ja) * 1987-11-14 1989-05-22 Nec Yamagata Ltd 浮遊ゲート型不揮発性メモリの製造方法

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GB2081018B (en) * 1980-07-31 1985-06-26 Suwa Seikosha Kk Active matrix assembly for display device
US4483726A (en) * 1981-06-30 1984-11-20 International Business Machines Corporation Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
JPS58194799A (ja) * 1982-05-07 1983-11-12 Hitachi Ltd 単結晶シリコンの製造方法
GB2131407B (en) * 1982-11-12 1987-02-04 Rca Corp Method of formation of silicon dioxide layer
GB2130009B (en) * 1982-11-12 1986-04-03 Rca Corp Polycrystalline silicon layers for semiconductor devices
US4592799A (en) * 1983-05-09 1986-06-03 Sony Corporation Method of recrystallizing a polycrystalline, amorphous or small grain material
JPS60202952A (ja) * 1984-03-28 1985-10-14 Fujitsu Ltd 半導体装置の製造方法
US4588447A (en) * 1984-06-25 1986-05-13 Rockwell International Corporation Method of eliminating p-type electrical activity and increasing channel mobility of Si-implanted and recrystallized SOS films
CA1239706A (en) * 1984-11-26 1988-07-26 Hisao Hayashi Method of forming a thin semiconductor film
US4597160A (en) * 1985-08-09 1986-07-01 Rca Corporation Method of fabricating a polysilicon transistor with a high carrier mobility
US4677250A (en) * 1985-10-30 1987-06-30 Astrosystems, Inc. Fault tolerant thin-film photovoltaic cell
JPS6310573A (ja) * 1986-07-02 1988-01-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4912540A (en) * 1986-12-17 1990-03-27 Advanced Micro Devices, Inc. Reduced area butting contact structure
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
US4897150A (en) * 1988-06-29 1990-01-30 Lasa Industries, Inc. Method of direct write desposition of a conductor on a semiconductor
US5180690A (en) * 1988-12-14 1993-01-19 Energy Conversion Devices, Inc. Method of forming a layer of doped crystalline semiconductor alloy material
NL9000324A (nl) * 1990-02-12 1991-09-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US5147826A (en) * 1990-08-06 1992-09-15 The Pennsylvania Research Corporation Low temperature crystallization and pattering of amorphous silicon films
US5169806A (en) * 1990-09-26 1992-12-08 Xerox Corporation Method of making amorphous deposited polycrystalline silicon thermal ink jet transducers
US5365875A (en) * 1991-03-25 1994-11-22 Fuji Xerox Co., Ltd. Semiconductor element manufacturing method
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
JP2508948B2 (ja) * 1991-06-21 1996-06-19 日本電気株式会社 半導体装置の製造方法
JP2855919B2 (ja) * 1991-10-24 1999-02-10 日本電気株式会社 半導体装置およびその製造方法
JP3197036B2 (ja) * 1991-11-14 2001-08-13 鐘淵化学工業株式会社 結晶質シリコン薄膜の形成方法
JPH05234900A (ja) * 1992-02-19 1993-09-10 Nec Corp 半導体装置の製造方法
KR950010859B1 (ko) * 1992-09-29 1995-09-25 현대전자산업주식회사 박막 트랜지스터의 채널폴리 제조방법
US5444302A (en) 1992-12-25 1995-08-22 Hitachi, Ltd. Semiconductor device including multi-layer conductive thin film of polycrystalline material
US5326722A (en) * 1993-01-15 1994-07-05 United Microelectronics Corporation Polysilicon contact
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
JP3124473B2 (ja) * 1994-08-19 2001-01-15 セイコーインスツルメンツ株式会社 半導体装置とその製造方法
US5893949A (en) * 1995-12-26 1999-04-13 Xerox Corporation Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US5843811A (en) * 1996-04-10 1998-12-01 University Of Florida Method of fabricating a crystalline thin film on an amorphous substrate
US5773329A (en) * 1996-07-24 1998-06-30 International Business Machines Corporation Polysilicon grown by pulsed rapid thermal annealing
GB2322733A (en) * 1997-02-27 1998-09-02 Nec Corp Polysilicon electrodes for DRAM cells
US5879975A (en) * 1997-09-05 1999-03-09 Advanced Micro Devices, Inc. Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile
JP2000111952A (ja) * 1998-10-07 2000-04-21 Sony Corp 電気光学装置、電気光学装置用の駆動基板、及びこれらの製造方法
US6281559B1 (en) * 1999-03-03 2001-08-28 Advanced Micro Devices, Inc. Gate stack structure for variable threshold voltage
US6455903B1 (en) 2000-01-26 2002-09-24 Advanced Micro Devices, Inc. Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation
JP4655495B2 (ja) * 2004-03-31 2011-03-23 東京エレクトロン株式会社 成膜方法
KR100773123B1 (ko) * 2005-11-28 2007-11-02 주식회사 에이이티 2단계 증착에 의한 다결정 실리콘 박막의 형성 방법
CN103236400B (zh) * 2013-03-29 2015-07-08 京东方科技集团股份有限公司 低温多晶硅薄膜制作方法、薄膜晶体管制作方法
KR20160029236A (ko) * 2014-09-04 2016-03-15 삼성전자주식회사 반도체 장치 및 그 제조 방법

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US3533857A (en) * 1967-11-29 1970-10-13 Hughes Aircraft Co Method of restoring crystals damaged by irradiation
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US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation
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JPS4837232B1 (ja) * 1968-12-04 1973-11-09
US3730765A (en) * 1970-09-15 1973-05-01 Gen Electric Method of providing polycrystalline silicon regions in monolithic integrated circuits
US4087571A (en) * 1971-05-28 1978-05-02 Fairchild Camera And Instrument Corporation Controlled temperature polycrystalline silicon nucleation
US3811076A (en) * 1973-01-02 1974-05-14 Ibm Field effect transistor integrated circuit and memory
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US3900345A (en) * 1973-08-02 1975-08-19 Motorola Inc Thin low temperature epi regions by conversion of an amorphous layer
US4123300A (en) * 1977-05-02 1978-10-31 International Business Machines Corporation Integrated circuit process utilizing lift-off techniques
US4134125A (en) * 1977-07-20 1979-01-09 Bell Telephone Laboratories, Incorporated Passivation of metallized semiconductor substrates
US4226898A (en) * 1978-03-16 1980-10-07 Energy Conversion Devices, Inc. Amorphous semiconductors equivalent to crystalline semiconductors produced by a glow discharge process
NL7810549A (nl) * 1978-10-23 1980-04-25 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting.
US4249968A (en) * 1978-12-29 1981-02-10 International Business Machines Corporation Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers
DE2932569C2 (de) * 1979-08-10 1983-04-07 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6448411A (en) * 1987-08-18 1989-02-22 Fujitsu Ltd Forming method of polysilicon layer
JPH01129465A (ja) * 1987-11-14 1989-05-22 Nec Yamagata Ltd 浮遊ゲート型不揮発性メモリの製造方法

Also Published As

Publication number Publication date
EP0051249A2 (en) 1982-05-12
DE3176714D1 (en) 1988-05-26
EP0051249A3 (en) 1985-04-24
US4358326A (en) 1982-11-09
JPS647488B2 (ja) 1989-02-09
EP0051249B1 (en) 1988-04-20

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