JPS5787165A - Semiconductor memory storage - Google Patents
Semiconductor memory storageInfo
- Publication number
- JPS5787165A JPS5787165A JP55163933A JP16393380A JPS5787165A JP S5787165 A JPS5787165 A JP S5787165A JP 55163933 A JP55163933 A JP 55163933A JP 16393380 A JP16393380 A JP 16393380A JP S5787165 A JPS5787165 A JP S5787165A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- blanking
- wafting
- pair
- manner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005055 memory storage Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 238000000034 method Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE: To contrive high density of EPROM which electrically performs a writing and a blanking operations by a method wherein a blanking gate and a limiting gate are cross-arranged on the substrate through the intermediary of an insulating film, and a pair of wafting gates are arranged on both sides of the blanking gate in such a manner that the terminal sections of the wafting gate will be superposed.
CONSTITUTION: A blanking gate 14 is provided on the field film 13 of a P-substrate 11, and a limiting gate 18A and a grounding diffusion layer 19C, to be used as a source region, are extendedly provided in such a manner that they are orthogonally intersecting. In the FET region on both sides of the blanking gate 14, wafting gates 15a and 15b, which are passing above the gate films 12a and 12b, are formed as a pair with 2-bis and symmetrically arranged. Also, a drain region 19A is connected to an Al digit line 21A, but it is to be constituted in such a manner that it will be in common with a pair of FET having gate films 15a and 15c. Through these procedures, the EPROM of one bit and one element structure, consisting of a source region 19A, a drain region 19C, and a wafting gate 15a, limiting gate 18A and a blanking gate 14, can be formed in high density.
COPYRIGHT: (C)1982,JPO&Japio
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55163933A JPS5787165A (en) | 1980-11-20 | 1980-11-20 | Semiconductor memory storage |
EP81305349A EP0052982B1 (en) | 1980-11-20 | 1981-11-11 | Semiconductor memory device and method for manufacturing the same |
DE8181305349T DE3175125D1 (en) | 1980-11-20 | 1981-11-11 | Semiconductor memory device and method for manufacturing the same |
US06/321,322 US4803529A (en) | 1980-11-20 | 1981-11-13 | Electrically erasable and electrically programmable read only memory |
US07/193,079 US4910565A (en) | 1980-11-20 | 1988-05-12 | Electrically erasable and electrically programmable read-only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55163933A JPS5787165A (en) | 1980-11-20 | 1980-11-20 | Semiconductor memory storage |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5787165A true JPS5787165A (en) | 1982-05-31 |
JPS6139753B2 JPS6139753B2 (en) | 1986-09-05 |
Family
ID=15783577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55163933A Granted JPS5787165A (en) | 1980-11-20 | 1980-11-20 | Semiconductor memory storage |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5787165A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4012757A (en) * | 1975-05-05 | 1977-03-15 | Intel Corporation | Contactless random-access memory cell and cell pair |
JPS52106275A (en) * | 1976-03-03 | 1977-09-06 | Nec Corp | Floating type nonvoltile semiconductor memory element |
JPS5513901A (en) * | 1978-07-17 | 1980-01-31 | Hitachi Ltd | Fixed memory of semiconductor |
-
1980
- 1980-11-20 JP JP55163933A patent/JPS5787165A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4012757A (en) * | 1975-05-05 | 1977-03-15 | Intel Corporation | Contactless random-access memory cell and cell pair |
JPS52106275A (en) * | 1976-03-03 | 1977-09-06 | Nec Corp | Floating type nonvoltile semiconductor memory element |
JPS5513901A (en) * | 1978-07-17 | 1980-01-31 | Hitachi Ltd | Fixed memory of semiconductor |
Also Published As
Publication number | Publication date |
---|---|
JPS6139753B2 (en) | 1986-09-05 |
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