JPS5787163A - Semiconductor memory storage - Google Patents

Semiconductor memory storage

Info

Publication number
JPS5787163A
JPS5787163A JP55163931A JP16393180A JPS5787163A JP S5787163 A JPS5787163 A JP S5787163A JP 55163931 A JP55163931 A JP 55163931A JP 16393180 A JP16393180 A JP 16393180A JP S5787163 A JPS5787163 A JP S5787163A
Authority
JP
Japan
Prior art keywords
gate
blanking
wafting
gates
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55163931A
Other languages
Japanese (ja)
Other versions
JPS6139752B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55163931A priority Critical patent/JPS5787163A/en
Priority to EP81305349A priority patent/EP0052982B1/en
Priority to DE8181305349T priority patent/DE3175125D1/en
Priority to US06/321,322 priority patent/US4803529A/en
Publication of JPS5787163A publication Critical patent/JPS5787163A/en
Publication of JPS6139752B2 publication Critical patent/JPS6139752B2/ja
Priority to US07/193,079 priority patent/US4910565A/en
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable to perform a homopolarized blanking and writing as well as to obtain high degree of integration for EPROM for the subject semiconductor memory storage by a method wherein a wafting gate and a blanking gate are provided in parallel with each other on the insulating film which are pinched between a substrate and a control gate, and these gates are superposed on a field region through the intermediary of the insulating film.
CONSTITUTION: Gate films 12a∼12d are provided in matrix form on the P type substrate, and drain regions 19A and 19B, to be connected to an Al digit wire 31, and a source region 19C to be grounded are formed by diffusion. On the field region 13, the blanking gate 14, consisting of the first layer polycrystalline Si, is provided as a blanking line 33, and wafting gates 15a∼15d are formed with the polycrystaline layer in such a manner that the terminal position of the gates will be superposed on the blanking gates by extending on the wafting gate. Control gates 18A and 18B of the third polycrystalline layer are extended on the wafting gate, and are formed as selective wires 35 and 36. The region surrounded by ABCD constitutes 1 bit, a writing operation is performed by applying positive polarity high voltage to lines 31 and 35, and by injecting hot carrier to the wafting gate, and the blanking is performed by grounding the lines 31 and 35, by applying a positive high voltage pulse to the blanking line 33 and by field-emitting the accumulated electron on the wafting gate to the blanking line 33.
COPYRIGHT: (C)1982,JPO&Japio
JP55163931A 1980-11-20 1980-11-20 Semiconductor memory storage Granted JPS5787163A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55163931A JPS5787163A (en) 1980-11-20 1980-11-20 Semiconductor memory storage
EP81305349A EP0052982B1 (en) 1980-11-20 1981-11-11 Semiconductor memory device and method for manufacturing the same
DE8181305349T DE3175125D1 (en) 1980-11-20 1981-11-11 Semiconductor memory device and method for manufacturing the same
US06/321,322 US4803529A (en) 1980-11-20 1981-11-13 Electrically erasable and electrically programmable read only memory
US07/193,079 US4910565A (en) 1980-11-20 1988-05-12 Electrically erasable and electrically programmable read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163931A JPS5787163A (en) 1980-11-20 1980-11-20 Semiconductor memory storage

Publications (2)

Publication Number Publication Date
JPS5787163A true JPS5787163A (en) 1982-05-31
JPS6139752B2 JPS6139752B2 (en) 1986-09-05

Family

ID=15783540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163931A Granted JPS5787163A (en) 1980-11-20 1980-11-20 Semiconductor memory storage

Country Status (1)

Country Link
JP (1) JPS5787163A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63266884A (en) * 1987-04-24 1988-11-02 Toshiba Corp Nonvolatile semiconductor memory
US7907451B2 (en) 2008-12-08 2011-03-15 Empire Technology Development Llc Semiconductor storage device and method of manufacturing same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106275A (en) * 1976-03-03 1977-09-06 Nec Corp Floating type nonvoltile semiconductor memory element
JPS5513901A (en) * 1978-07-17 1980-01-31 Hitachi Ltd Fixed memory of semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106275A (en) * 1976-03-03 1977-09-06 Nec Corp Floating type nonvoltile semiconductor memory element
JPS5513901A (en) * 1978-07-17 1980-01-31 Hitachi Ltd Fixed memory of semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63266884A (en) * 1987-04-24 1988-11-02 Toshiba Corp Nonvolatile semiconductor memory
US7907451B2 (en) 2008-12-08 2011-03-15 Empire Technology Development Llc Semiconductor storage device and method of manufacturing same

Also Published As

Publication number Publication date
JPS6139752B2 (en) 1986-09-05

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