JPS6139752B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a memory cell of a programmable ROM in which data can be electrically erased.

EP-POM (Erasable Programmable-ROM)
Data can be written or erased after manufacturing, and there are two main types: ultraviolet erasable type and electrically erased type. Among these, UV-erasable EP-ROM has one memory cell.
Since it can be configured with one transistor, it is possible to achieve high integration, and to date, devices with 32K bits and 64K bits of integration have been developed. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable P-ROM)
(referred to as ROM), one memory cell consists of at least two transistors, so the degree of integration cannot be increased very high, and so far only 16K bits of integration have been announced.
However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure, 1 is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point is a MOS transistor 4 for bit selection.
and a double gate type MOS transistor 5 having a control gate and a floating gate for data storage are connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2, and the control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is made up of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

An object of the present invention is to provide a semiconductor memory device that can eliminate the above-mentioned drawbacks.

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a to 2d show the configuration of 4-bit memory cells of a semiconductor memory device according to the present invention, FIG. 2a is a pattern plan view, and FIG. 2b is a pattern plan view.
is a structural cross-sectional view taken along line -' in figure a, Figure 2 c is a structural cross-sectional view taken along line -' in figure a, and
Figure d is a structural sectional view taken along the line -' in figure a.

In FIG. 2, reference numeral 11 denotes a semiconductor substrate made of P-type silicon. On the surface of this substrate 11, gate insulating films 12a, 12b, 12c, and 12d are arranged at regular intervals in an XY matrix.
Further, on the surface of the substrate 11, two gate insulating films 12a and 12 are formed adjacent to each other in the vertical direction in the figure.
c, 12b and 12d are paired, and a field insulating film 13 is formed between the pair of gate insulating films. Moreover, on this field insulating film 13, P
Alternatively, a first conductor layer 14 made of polysilicon containing As is formed. Furthermore, each of the gate insulating films 12a, 12b, 12c, 12d
Above, second conductive layers 15a, 15b, 15c, and 15d made of polysilicon are formed separately from each other. 2 located on the left side of the first conductor layer 14 in the figure.
The right end portions of the second conductive layers 15a and 15c overlap the left end portions of the first conductive layer 14 with the insulating film 16 interposed therebetween. Further, the left end portions of the two second conductive layers 15b and 15d located on the right side with respect to the conductive layer 14 are connected to the right end portions of the conductive layer 14 via the insulating film 16. It overlaps with Furthermore, second conductor layers 15a and 1 adjacent in the left and right direction in the figure
A third conductor layer 18A made of polysilicon and having a width set to be approximately the same as both conductor layers 15a and 15b is formed on the conductor layer 5b via an insulating film 17 so as to cover it. Similarly, the second conductor layer 1 adjacent in the left and right direction in the figure
5c, 15d are covered with conductive layers 15c, 15d via the insulating film 17.
Another third conductor layer 18B made of polysilicon and having a width set to be approximately the same as that is formed. And also, 2 adjacent vertically in the figure
An N ⁺ type semiconductor layer 19A is formed in the surface region of the substrate 11 between the gate insulating films 12a and 12c at two locations, and similarly, the gate insulating film 12 at two locations
In the surface area of the substrate 11 between b and 12d,
An N ⁺ type semiconductor layer 19B is formed. Furthermore, each gate insulating film 12a, 12b, 12c, 12d
In contrast, the N ⁺ type semiconductor layer 19A or 1
A continuous N ⁺ type semiconductor layer 19C is formed in the surface region of the substrate 11 on the side opposite to the side where the layer 9B is formed. Further, the third conductive layer 18A, 18
A fourth layer made of Al is placed on B with an insulating film 20 interposed therebetween.
Conductive layers 21A and 21B are formed, one of which is connected to the N + type semiconductor layer 19A by a contact portion 22A, and the other conductive layer 21B is connected to the N ⁺ type semiconductor layer 19A by a contact portion 22A. Another contact portion 2 is the N ⁺ type semiconductor layer 19B.
2B. The N ⁺ type semiconductor layer 19C is connected to a reference potential point, for example, a ground potential point.

Furthermore, in FIG. 2a, the area surrounded by broken lines and marked with the symbol ABCD indicates a memory cell for one bit of this semiconductor memory device, and as is clear from FIG. 2b, this memory cell is The second conductive layer 15 is a floating gate, the third conductive layer 18 is a control gate, and the first conductive layer 14 is an erase gate. ) as shown in Figure 2b.
When looking at the bits, the control gate and erase gate mentioned above are common, and a pair of symmetrical structures with respect to the erase gate are used.
It consists of MOS transistors. The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel in the insulating film sandwiched between the control gate and the substrate 11. There is. Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 2b, in the overlapping portion, the second conductor layer 15, ie, the floating gate, is located above the first conductor layer 14, ie, the erase gate. , the distance between the substrate 11 and the conductor layer 14 is shorter than the distance between the substrate 11 and the conductor layer 15.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, 31 and 32 are digit lines made up of the fourth conductive layers 21A and 21B, 33 and 34 are erase lines formed by extending the first conductive layer 14, and 35, 36
is a selection line formed by extending the third conductor layers 18A and 18B. Also M1 to M4
is a memory cell, each memory cell is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D, and a source S. The drains D of the memory cells M1 and M2 are connected to one of the digit lines 31 and Cell M3,
The drain D of M4 is connected to the other digit line 32,
The sources S of all memory cells are respectively connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now paying attention to memory cell M1 in FIG. 3, in the initial state the floating gate of this memory cell M1 is
No electrons are injected into FG, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, by applying a positive high voltage, e.g., +20 volts, to the selection line 35 and a positive high voltage, e.g., +20 volts, to the digit line 31,
A flow of hot electrons occurs from the source S to the drain D of the memory cell M1, and these hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1.
Note that during data writing, the erase line 33 may be applied with a pulse of a high voltage, for example, +20 volts, or may be applied with a DC voltage of +5 volts or 0 volts, or may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and the memory cell M
High level signal (+5
voltage) is applied. When this high level signal is applied, if the threshold voltage V _TH is low, this memory cell M1 is turned on and one digit line 31 is turned on.
A current flows from the memory cell M1 toward the ground potential point. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows. At this time, the state in which current flows through the memory cell M1 is a logic "1" level, and the state in which no current flows is a logic "0" level.
level, this device can be used as a storage device. Also floating gate
As mentioned above, the FG is surrounded by an insulating film and is isolated from other parts, so the electrons once injected here cannot escape during normal use. Therefore, it can be used as a non-volatile data storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, field emission occurs between the floating gate FG and the erase gate EG of the memory cell M1, and the electrons that had been accumulated in the floating gate FG are removed. is leaked to the outside via the erase gate EG and the erase line 33. As a result, the threshold voltage V _TH of this memory cell M1 returns to a low state similar to the initial state.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP--
As a ROM, it is possible to realize an ultraviolet erasable ROM with the same degree of integration. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and reading data can be performed using a single polarity power supply. That is, +20 volts when writing and +20 volts when erasing.
When reading 40 volts, you only need a +5 volt positive power supply, and if you use a booster circuit to obtain +20 volts and +40 volts from the +5 volt voltage, you can use only one +5 volt power supply. can. Therefore, data can be written, erased, and read while mounted on a printed wiring board or the like.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since no other process is required except for forming a three-layer polysilicon structure, the product can be manufactured using a normal silicon gate process.

Moreover, in the memory device of the above embodiment, by arranging and forming the erase gate on a plane different from that of the control gate, it is possible to integrate a plurality of memory cells, compared to the case where the erase gate and the control gate are arranged and formed on the same plane. Since the erase gate and the control gate can be provided to cross each other, as shown in FIG. 2, for example, when circuiting, a plurality of memory cells can be easily arranged in a matrix.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 2 will be described with reference to pattern plan views shown in FIGS.
The explanation will be made using cross-sectional views taken along the lines ``-'' to ``e''. First, Figure 4a and Figure 5a
As shown in FIG. 2, field insulating films 13 and 13' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography.
Further, P or As is diffused into the shaded area in FIG. 4a by implantation or diffusion to form an N-type semiconductor layer 19C'. After the completion of the above diffusion, the above field insulating film 1
After exposing the surface of the substrate 11 in areas other than the forming areas 3 and 13', thermal oxidation is applied to this area using a thermal oxidation method to form a relatively thin film of 1000 to 2000 Å for forming the gate insulating film 12. A film 23 is formed. Next, polysilicon with a thickness of 6000 Å is grown on the entire substrate 11, and after doping it with P or As, a first conductor layer is formed in the solid line area in FIG. 4b by photolithography. Form 14. Here, a side is shown in which the first conductive layer 14 is not formed on the adjacent field insulating films 13', but this may be formed if necessary. Next, after forming the first conductive layer, as shown in FIG. 4c and FIG.
A polysilicon film with a thickness of 5000 Å was grown by the CVD method, and a second conductor layer 15a as a floating gate was grown by applying a photolithography method.
15b, 15c, and 15d are formed. Here the fifth
As is clear from the figure, in FIG. An example is shown in which at least a portion thereof overlaps with the conductor layer 14. Regarding the other ends of the conductor layers 15a and 15b, the conductor layer 1
It does not overlap with 4. After forming the floating gate, as shown in FIGS. 4d and 5d,
Insulating film 1 with a thickness of 1000 to 2000 Å by thermal oxidation method
7 is formed, polysilicon is deposited thereon, and a photolithography method is applied to this to form third conductor layers 18A and 18B which will become control gates, and at the same time, a second conductor layer is formed. layers 15a, 15b,
15c and 15d are formed by self-alignment. Next, P or As is diffused into the shaded areas in ^FIG .
B, 19C is formed. Further, as shown in FIGS. 4e and 5e, an insulating film 20 is formed over the entire substrate 11.
and an Al film are successively deposited, and a photolithography method is applied to this Al film to form a fourth conductor layer 21A,
21B and the contact portion 22
A, 22B makes the N ⁺ type semiconductor layer 19A,
This semiconductor memory device is completed by connecting each of 19B.

Note that the present invention is not limited to the above-mentioned embodiments; for example, only the right end portion or the left end portion of the second conductive layer 15 is at least a portion of the first conductive layer 14. Although a case has been described in which the conductive layer 15 is overlapped with the conductor layer 15, the structure may be such that the conductor layer 15 overlaps each other at both ends thereof.
Further, although the first conductive layer 14 and the second conductive layer 15 are both made of polysilicon, molybdenum may be used instead.

As ^explained above, in the semiconductor memory device of the present invention, one memory cell can be configured with one transistor, and data can be electrically erased. Many effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one memory cell portion of a conventional E ² -P-ROM, FIGS. 2 a to d show a semiconductor memory device according to the present invention, and FIG. 2 a is a pattern plan view. , Figure 2 b is the same figure as -
Figure 2c is a structural cross-sectional view taken along line -' in figure a, Figure 2d is a structural cross-sectional view taken along line -' in figure a, and Figure 3 is a structural cross-sectional view taken along line -' in figure a. The equivalent circuit diagrams of the apparatus shown in FIGS. 4a to 5e and 5a to 5e are for explaining an example of a manufacturing method for manufacturing the apparatus shown in FIG. Figures a to e are pattern plan views, and Figures 5a to 5e are sectional views taken along the lines -' of Figures 4a to 4e. 11... Semiconductor substrate, 12... Gate insulating film, 13
...Field insulating film, 14...First conductor layer (erase gate), 15...Second conductor layer (floating gate), 16, 17, 20...Insulating film, 18...Third layer Eye conductor layer (control gate), 19...N ⁺ type semiconductor layer, 21... Fourth conductor layer, 22... Contact portion, 23... Thermal oxide film, 31, 32... Digit line, 33, 34 …
Erasure line, 35, 36...selection line, M1, M2, M
3, M4...memory cell, CG...control gate, FG...floating gate, EG...erase gate, D...drain, S...source.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate, a control gate provided on the substrate via an insulating film, a floating gate provided in parallel within the insulating film sandwiched between the control gate and the substrate, and What is claimed is: 1. A semiconductor memory device comprising: an erase gate; 2. The semiconductor memory device according to claim 1, wherein the floating gate and the erase gate partially overlap with each other with an insulating film interposed therebetween. 3. The semiconductor memory device according to claim 2, wherein the overlapping portion is within a field region. 4. According to claim 2, the distance between the erase gate and the base body is set to be shorter than the distance between the floating gate and the base body in the overlapping portion of the floating gate and the erase gate. The semiconductor storage device described above. 5. The semiconductor memory device according to claim 1, wherein both the floating gate and the erase gate are made of polysilicon. 6. The semiconductor memory device according to claim 1, wherein the floating gate and the erase gate are both made of molybdenum.